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Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors (2001)
| Citations: | 82 - 0 self |
BibTeX
@INPROCEEDINGS{Michaud01data-flowprescheduling,
author = {Pierre Michaud and Andre Seznec},
title = {Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors},
booktitle = {},
year = {2001},
pages = {27--36}
}
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Abstract
The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue buffer. Determining which instructions from the issue buffer can be launched to the execution units is a timecritical operation which complexity increases with the issue buffer size. We propose to relieve the issue stage by reordering instructions before they enter the issue buffer. This study introduces the general principle of data-flow prescheduling. Then we describe a possible implementation. Our preliminary results show that data-flow prescheduling makes it possible to enlarge the effective instruction window while keeping the issue buffer small. 1. Introduction Processor performance is strongly correlated with the clock cycle. Shorter clock cycle has been allowed by both improvements in silicon technology and careful processor design. As a consequence of this evolution, the IPC (average number of ins...
Keyphrases
data-flow prescheduling out-of-order processor issue buffer large instruction window conventional processor careful processor design issue buffer size preliminary result effective instruction window execution unit average number introduction processor performance instruction window size possible implementation shorter clock cycle effective instruction window cannot general principle issue stage timecritical operation silicon technology clock cycle
