DMCA
A comprehensive instruction fetch mechanism for a processor supporting speculative execution (1992)
Cached
Download Links
- [www.hadassah-col.ac.il]
- [www.geocities.com]
- [www.ece.utexas.edu]
- DBLP
Other Repositories/Bibliography
| Venue: | IN PROCEEDINGS OF THE 25TH ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE |
| Citations: | 68 - 5 self |
BibTeX
@INPROCEEDINGS{Yeh92acomprehensive,
author = {Tse-Yu Yeh and Yale N. Patt},
title = {A comprehensive instruction fetch mechanism for a processor supporting speculative execution},
booktitle = {IN PROCEEDINGS OF THE 25TH ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE},
year = {1992},
pages = {129--139},
publisher = {}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
A superscalar processor supporting speculative execution requires an instruction fetch mechanism that can provide instruction fetch addresses as nearly correct as possible and as soon as possible in order to reduce the likelihood of throwing away speculative work. In this paper we propose a comprehensive instruction fetch mechanism to satisfy that need. Implementation issues are identified, possible solutions and designs for resolving those issues are simulated, and the results of these simulations are presented. A metric for measuring the average penalty of executing a branch instruction is introduced and used to evaluate the performance of our instruction fetch mechanism. We achieve an average performance of 4.19 IPC on the original SPEC benchmarks in a machine which can execute ve instructions ideally by using the proposed mechanism.
Keyphrases
speculative execution comprehensive instruction fetch mechanism instruction fetch mechanism ve instruction branch instruction implementation issue average penalty instruction fetch address possible solution superscalar processor average performance original spec benchmark speculative work
