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Variable packet size buffered crossbar (cicq) switches (2004)
| Venue: | In Proceedings, IEEE International Conference on Communications (ICC 2004 |
| Citations: | 29 - 7 self |
BibTeX
@INPROCEEDINGS{Katevenis04variablepacket,
author = {Manolis Katevenis and Georgios Passas and Dimitrios Simos and Ioannis Papaefstathiou and Nikos Chrysos},
title = {Variable packet size buffered crossbar (cicq) switches},
booktitle = {In Proceedings, IEEE International Conference on Communications (ICC 2004},
year = {2004},
pages = {1090--1096}
}
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Abstract
Abstract — One of the most widely used architectures for packet switches is the crossbar. A special version of it is the buffered crossbar, where small buffers are associated with the crosspoints; this simplifies scheduling and improves its efficiency and QoS capabilities to the point where the switch needs no internal speedup. Furthermore, by supporting variable length packets throughout a buffered crossbar: (a) there is no need for segmentation and reassembly (SAR) circuits; (b) no speedup is necessary to support SAR; and (c) synchronization between the input and output clock domains is simplified. In turn, the lack of SAR and speedup mean that no output queues are needed, either. In this paper we present an architecture, a chip layout and cost analysis, and a performance evaluation of such a 300 Gbps buffered crossbar operating on variable-size packets. The proposed organization is simple yet powerful, can be implemented using modern technology, and, as the performance results demonstrate, it clearly outperforms unbuffered crossbars. 1
Keyphrases
variable packet size buffered crossbar packet switch variable length packet modern technology cost analysis output queue speedup mean used architecture variable-size packet chip layout internal speedup small buffer performance evaluation output clock domain performance result unbuffered crossbar qos capability special version
