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A Parametric Study of Scalable Interconnects on FPGAs
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BibTeX
@MISC{Wang_aparametric,
author = {Daihan Wang and Hiroki Matsutani and Masato Yoshimi and Michihiro Koibuchi and Hideharu Amano},
title = {A Parametric Study of Scalable Interconnects on FPGAs},
year = {}
}
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Abstract
Abstract — With the constantly increasing gate capacity of FP-GAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, Network-On-Chip (NoC), in which different flows share a point-to-point link, becomes advantageous in terms of scalability. Although fixed regular network infrastructures are only used in recent FPGAbased NoCs, the network topology can be optimized to fit the target application on FPGAs. In this paper, we investigate the suitable interconnects based on the typical implementation of NoC router with various number of wires per channel on FPGAs. In order to clearly illustrate the trade-off between network throughput and hardware amount for network components, we evaluate the amount of hardware for various networks, which are composed by routers with different port numbers, and their throughput using a flitlevel simulation. Evaluation results show that for small systems with 16 cores or less, a large router is advantageous from the viewpoint of both performance and cost. On the other hand, when systems become large, the partitioned networks are efficient from the viewpoint of cost. Keywords: Network-on-chip, FPGA, router, node degree, simulation I.
Keyphrases
parametric study scalable interconnects fixed regular network infrastructure target application various number suitable interconnects large number flitlevel simulation small system different port number hardware amount single fpga chip gate capacity different flow share recent fpgabased noc typical implementation various network large-scale application large router network topology node degree point-to-point link noc router network component evaluation result network throughput computational node
