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Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks
| Citations: | 4 - 0 self |
BibTeX
@MISC{Hämäläinen_reviewof,
author = {Panu Hämäläinen and Marko Hännikäinen and Timo D. Hämäläinen},
title = {Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks},
year = {}
}
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Abstract
Abstract. Wireless Sensor Networks (WSN) are seen as attractive solutions for various monitoring and controlling applications, a large part of which require cryptographic protection. Due to the strict cost and power consumption requirements, their cryptographic implementations should be compact and energy-efficient. In this paper, we survey hardware architectures proposed for Advanced Encryption Standard (AES) implementations in low-cost and low-power devices. The survey considers both dedicated hardware and specialized processor designs. According to our review, currently 8-bit dedicated hardware designs seem to be the most feasible solutions for embedded, low-power WSN nodes. Alternatively, compact special functional units can be used for extending the instruction sets of WSN node processors for efficient AES execution. 1
Keyphrases
hardware architecture low-power device efficient aes execution survey hardware architecture cryptographic implementation low-power wsn node wireless sensor network dedicated hardware various monitoring instruction set advanced encryption standard wsn node processor attractive solution compact special functional unit cryptographic protection strict cost specialized processor design feasible solution power consumption requirement large part
