CiteSeerX — Exploring the Design Space of Future CMPs

DMCA

Exploring the Design Space of Future CMPs

Cached

Download Links

Other Repositories/Bibliography

DBLP

by Unknown Authors

BibTeX

@MISC{_exploringthe,
    author = {},
    title = {Exploring the Design Space of Future CMPs},
    year = {}
}

OpenURL

Abstract

In this paper, we study the space of chip multiprocessor (CMP) organizations. We compare the area and performance trade-offs for CMP implementations to determine how many processing cores future server CMPs should have, whether the cores should have in-order or out-oforder issue, and how big the per-processor on-chip caches should be. We find that, contrary to some conventional wisdom, out-of-order processing cores will maximize job throughput on future CMPs. As technology shrinks, limited off-chip bandwidth will begin to curtail the number of cores that can be effective on a single die. Current projections show that the transistor/signal pin ratio will increase by a factor of 45 between 180 and 35 nanometer technologies. That disparity will force increases in per-processor cache capacities as technology shrinks, from 128KB at 100nm, to 256KB at 70nm, and to 1MB at 50 and 35nm, reducing the number of cores that would otherwise be possible. 1

Keyphrases

future cmps design space technology shrink transistor signal pin ratio limited off-chip bandwidth single die cmp implementation performance trade-off out-oforder issue current projection out-of-order processing core chip multiprocessor per-processor on-chip cache many processing core conventional wisdom nanometer technology job throughput per-processor cache capacity