DMCA
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs (1991)
| Venue: | In Proceedings of International Test Conference |
| Citations: | 44 - 15 self |
BibTeX
@INPROCEEDINGS{Ferguson91testpattern,
author = {Joel Ferguson and Tracy Larrabee},
title = {Test Pattern Generation for Realistic Bridge Faults in CMOS ICs},
booktitle = {In Proceedings of International Test Conference},
year = {1991},
pages = {492--499},
publisher = {IEEE}
}
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Abstract
Two approaches have been used to balance the cost of generating effective tests for IC's and the need to increase the quality level of shipped IC's. The first approach favors using high-level fault models to reduce test generation costs, and the second approach favors the use of low-level, technology-specific fault models that lead to high test generation costs, but increased defect coverage in the tested circuits. In this paper we simulate complete single stuck-at test sets against a low-level model of bridge defects showing that an unacceptably high percentage of such defects are not detected by the complete stuck-at test sets. Next, we show how low-level bridge fault models can be incorporated into high-level test generation. Finally, we describe our system for generating effective tests for bridge faults and report on its performance. 1 Motivation The goal of a production testing system is to cost effectively minimize the number of bad parts that pass the tests. The number of bad ...
Keyphrases
test pattern generation cmos ic realistic bridge fault effective test bad part first approach favor complete single stuck-at test set high-level test generation low-level bridge fault model defect coverage bridge defect complete stuck-at test set high test generation cost quality level bridge fault high-level fault model low-level model shipped ic second approach favor test generation cost high percentage tested circuit technology-specific fault model
