Bounded model checking

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Bounded model checking (2009)

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by Armin Biere

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165 - 3 self

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@MISC{Biere09boundedmodel,
    author = {Armin Biere},
    title = {Bounded model checking},
    year = {2009}
}

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Abstract

Besides Equivalence Checking [KK97, KPKG02] the most important industrial application of SAT is currently Bounded Model Checking (BMC) [BCCZ99]. Both techniques are used for formal hardware verification in the context of electronic design automation (EDA), but have successfully been applied to many other domains as well. In this chapter, we focus on BMC. In practice, BMC is mainly used for falsification resp. testing, which is concerned with violations of temporal properties. However, the original paper on BMC [BCCZ99] already discussed extensions that can prove properties. A considerable part of this chapter discusses these complete extensions, which are often called “unbounded ” model checking techniques, even though they are build upon the same principles as plain BMC. Two further related applications, in which BMC becomes more and more important, are automatic test case generation for closing coverage holes, and disproving redundancy in designs. Most of the techniques discussed in this chapter transfer to this more general setting as well, even though our focus is on property

Keyphrases

many domain unbounded model coverage hole chapter transfer electronic design automation bmc bccz99 automatic test case generation complete extension general setting related application falsification resp model checking original paper temporal property important industrial application considerable part equivalence checking kk97 formal hardware verification plain bmc

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