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An Embedded Processor with Instruction Packing
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BibTeX
@MISC{Satayavibul_anembedded,
author = {C. Satayavibul and P. Chongstitvatana},
title = {An Embedded Processor with Instruction Packing},
year = {}
}
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Abstract
Abstract- This work proposes a design of, SX4, a resource efficient 32-bit processor. SX4 is designed for a limited resource embedded system. The performance of SX4 has been improved by the "instruction packing " method. The measurement on the performance improvement is evaluated. Instruction packing reduces the code size by 33.0 % at the same time it improve the speed of the processor by 17.1%. The proposed design has been realized on a FPGA device. SX4 processor requires 10,020 equivalent gates. Its maximum frequency is 63 MHz. In term of cycle consumed, it compares very well to commercial 32-bit Xilinx's microprocessor, Micro Blaze. I.
