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Wattch: A Framework for Architectural-Level Power Analysis and Optimizations (2000)
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| Venue: | In Proceedings of the 27th Annual International Symposium on Computer Architecture |
| Citations: | 1319 - 43 self |
BibTeX
@INPROCEEDINGS{Brooks00wattch:a,
author = {David Brooks and Vivek Tiwari and Margaret Martonosi},
title = {Wattch: A Framework for Architectural-Level Power Analysis and Optimizations},
booktitle = {In Proceedings of the 27th Annual International Symposium on Computer Architecture},
year = {2000},
pages = {83--94}
}
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Abstract
Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.
