BibTeX
@MISC{_poweroptimization,
author = {},
title = {Power Optimization Technique for testing VLSI Circuits},
year = {}
}
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Abstract
circuit were proposed. It eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. In this method over than existing single cycle access. This method is backward compatible to full scan designs and existing test pattern generators. The simulators can be used with a minor enhancement on this system. The Experimental measurement of design performance in terms of area, speed, power for single cycle access test structure implementation is presented. In this proposed approach were give an efficient power support to the structure achieved by Finite State Machine (FSM).
Keyphrases
vlsi circuit power optimization technique peak power consumption problem experimental measurement functional mode test pattern generator full scan design finite state machine design performance minor enhancement capture cycle efficient power support conventional shift-based scan chain complete test single cycle access
