Expandable networks for neuromorphic chips

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Expandable networks for neuromorphic chips (2007)

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by Paul A. Merolla , John V. Arthur , Bertram E. Shi , Kwabena A. Boahen

Venue:	IEEE Trans. Circuits Syst. I
Citations:	15 - 4 self

BibTeX

@ARTICLE{Merolla07expandablenetworks,
    author = {Paul A. Merolla and John V. Arthur and Bertram E. Shi and Kwabena A. Boahen},
    title = {Expandable networks for neuromorphic chips},
    journal = {IEEE Trans. Circuits Syst. I},
    year = {2007},
    pages = {301--311}
}

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Abstract

Abstract — We have developed a grid network that broadcasts spikes (binary events) in a multi-chip neuromorphic system by relaying them from chip to chip. The grid is expandable because, unlike a bus, its capacity does not decrease as more chips are added. The multiple relays do not increase latency because the grid’s cycle-time is shorter than the bus. We describe an asynchronous relay implementation that automatically assigns chip-addresses to indicate the source of spikes, encoded as wordserial address-events. This design, which is integrated on each chip, connects neurons at corresponding locations on each of the chips (pointwise connectivity) and supports oblivious, targeted, and excluded delivery of spikes. Results from two chips fabricated in 0.25-µm technology are presented, showing word-rates up to 45.4 M events/s. I. ADDRESS-EVENT COMMUNICATION

Keyphrases

expandable network neuromorphic chip multi-chip neuromorphic system binary event connects neuron multiple relay asynchronous relay implementation address-event communication wordserial address-events grid network grid cycle-time

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