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A refinement approach to design and verification of on-chip communication protocols (2008)
| Venue: | in 2008 Formal Methods in Computer Aided Design, A. Cimatti and |
| Citations: | 3 - 1 self |
BibTeX
@INPROCEEDINGS{Böhm08arefinement,
author = {Peter Böhm and Tom Melham},
title = {A refinement approach to design and verification of on-chip communication protocols},
booktitle = {in 2008 Formal Methods in Computer Aided Design, A. Cimatti and},
year = {2008},
pages = {136--143}
}
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Abstract
Abstract—Modern computer systems rely more and more on on-chip communication protocols to exchange data. To meet performance requirements these protocols have become highly complex, which usually makes their formal verification infeasible with reasonable time and effort. We present a new refinement approach to on-chip communication protocols that combines design and verification together, interleaving them hand-in-hand. Our modeling framework consists of design steps and design transformations formalized as finite state machines. Given a verified design step, transformations are used to extend the system with advanced features. A design transformation ensures that the extended design is correct if the previous system is correct. This approach is illustrated by an arbiter-based master-slave communication system inspired by the AMBA High-performance Bus architecture. Starting with a sequential protocol design, it is extended with pipelining and burst transfers. Transformations are generated from design constraints providing a basis for correctness-by-design of the derived system. I.
Keyphrases
on-chip communication protocol refinement approach design transformation performance requirement derived system previous system abstract modern computer system verified design step sequential protocol design design step formal verification design constraint arbiter-based master-slave communication system reasonable time advanced feature extended design new refinement approach amba high-performance bus architecture framework consists burst transfer finite state machine
