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GATE – a general architecture for text engineering (2004)
| Venue: | In Proceedings of the 16th Conference on Computational Linguistics (COLING96). http://citeseer.nj.nec.com/43097.html |
| Citations: | 2 - 1 self |
BibTeX
@INPROCEEDINGS{Fox04gate–,
author = {Anthony Fox},
title = {GATE – a general architecture for text engineering},
booktitle = {In Proceedings of the 16th Conference on Computational Linguistics (COLING96). http://citeseer.nj.nec.com/43097.html},
year = {2004}
}
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Abstract
The hol-4 proof system has been used to formally verify the correctness of the ARM6 micro-architecture. This paper describes the specification and verification of one instructions class, block data transfers; these are a form of load-store instruction in which a set of up to sixteen registers can be transferred atomically. The ARM6 is a commercial RISC microprocessor that has been used extensively in embedded systems – it has a 3-stage pipeline with a multi-cycled execute stage. A list based programmer’s model specification of the block data transfers is compared with the ARM6’s implementation which uses a 16-bit mask. The models are far removed and reasonably complex, and this poses a verification challenge. This paper describes the approach and some key lemmas used in verifying correctness, which is defined using data and temporal abstraction maps. 1
Keyphrases
text engineering general architecture block data transfer commercial risc microprocessor temporal abstraction map 16-bit mask 3-stage pipeline hol-4 proof system multi-cycled execute stage verification challenge key lemma load-store instruction arm6 micro-architecture sixteen register arm6 implementation embedded system instruction class
