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Tile Size Selection Using Cache Organization and Data Layout (1995)
| Citations: | 230 - 2 self |
BibTeX
@INPROCEEDINGS{Coleman95tilesize,
author = {Stephanie Coleman and Kathryn S. M Kinley},
title = {Tile Size Selection Using Cache Organization and Data Layout},
booktitle = {},
year = {1995},
pages = {279--290},
publisher = {ACM Press}
}
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Abstract
When dense matrix computations are too large to fit in cache, previous research proposes tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for choosing problem-size dependent tile sizes based on the cache size and cache line size for a direct-mapped cache. The algorithm eliminates both capacity and self-interference misses and reduces cross-interference misses. We measured simulated miss rates and execution times for our algorithm and two others on a variety of problem sizes and cache organizations. At higher set associativity, our algorithm does not always achieve the best performance. However on direct-mapped caches, our algorithm improves simulated miss rates and measured execution times when compared with previous work. 1 Introduction Due to the wide gap between processor and memory speed in current architectures, achieving good performance requires high cache efficiency. Compiler optimizations to improve data locality for uniprocessors is increas...
Keyphrases
data layout direct-mapped cache wide gap high cache efficiency previous research capacity miss reduces cross-interference miss dense matrix computation good performance compiler optimization self-interference miss measured execution time previous work miss rate cache size algorithm improves cache line size data locality simulated miss rate execution time set associativity problem-size dependent tile size current architecture cache organization introduction due memory speed problem size new algorithm
