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Programmable Active Memories: a Performance Assessment (1993)
| Venue: | Research on Integrated Systems: Proceedings of the 1993 Symposium |
| Citations: | 112 - 8 self |
BibTeX
@INPROCEEDINGS{Roncin93programmableactive,
author = {Bertin Roncin and P. Bertin and D. Roncin and J. Vuillemin},
title = {Programmable Active Memories: a Performance Assessment},
booktitle = {Research on Integrated Systems: Proceedings of the 1993 Symposium},
year = {1993},
pages = {88--102},
publisher = {MIT Press}
}
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Abstract
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [BRV 89]. Based on Programmable Gate Array (PGA) technology, the PAM is a universal hardware co-processor closely coupled to a standard host computer. The PAM can speed up many critical software applications running on the host, by executing part of the computations through a specific hardware PAM design. The performance measurements presented are based on two PAM architectures and ten specific applications, drawn from arithmetics, algebra, geometry, physics, biology, audio and video. Each of these PAM designs proves as fast as any reported hardware or super-computer for the corresponding application. In cases where we could bring some genuine algorithmic innovation into the design process, the PAM has proved an order of magnitude faster than any previously existing system (see [SBV 91] and [S 92]). 1 PAM concept Like any RAM memory module, a PAM is att...
Keyphrases
programmable active memory performance assessment specific hardware pam design corresponding application ram memory module pam architecture many critical software application quantitative performance measurement performance measurement standard host computer genuine algorithmic innovation universal hardware co-processor specific application pam concept programmable gate array design process
