BibTeX
@MISC{Sysoev_hardwareimplementation,
author = {Igor Sysoev and Ernst Gabidulin},
title = { HARDWARE IMPLEMENTATION OF RANK CODEC},
year = {}
}
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Abstract
The authors present a hardware implementation of the codec for rank codes. Parameters of rank code are (8,4,5). Algorithm was implemented on FPGA Spartan 3. Code rate is 1/2. The codec operates with elements from Galois field GF(2 8). The device can process informational data stream up to 77 MiB/s. Proposed results should help understanding rank code structure and simplify the problem of its application.
