DMCA
Breaking Address Mapping Symmetry at Multi-levels of Memory Hierarchy to Reduce DRAM Row-buffer Conflicts
| Citations: | 3 - 0 self |
BibTeX
@MISC{Zhang_breakingaddress,
author = {Zhao Zhang and Zhichun Zhu and Xiaodong Zhang},
title = {Breaking Address Mapping Symmetry at Multi-levels of Memory Hierarchy to Reduce DRAM Row-buffer Conflicts},
year = {}
}
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Abstract
DRAM row-buffers have become a critical level of cache in the memory hierarchy to exploit spatial locality in the cache miss stream. Row-buffer conflicts occur when a sequence of requests on different pages goes to the same memory bank, causing higher memory access latency than requests to the same row or to different banks. In this study, we first show that the address mapping symmetry between the cache and DRAM is the inherent source of row-buffer conflicts. Breaking the symmetry to reduce the conflicts and to retain the spatial locality, we propose and evaluate a permutation-based page interleaving scheme. We have also evaluated and compared two representative cache mapping schemes that break the symmetry at the cache level. We show that the proposed page interleaving scheme outperforms all other mapping schemes based on its overall performance and on its implementation simplicity. 1
Keyphrases
memory hierarchy dram row-buffer conflict address mapping symmetry row-buffer conflict spatial locality inherent source different page memory access latency scheme outperforms cache miss stream dram row-buffers permutation-based page overall performance representative cache mapping scheme implementation simplicity memory bank cache level different bank critical level
