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An efficient relaxation-based test . . . (2006)
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by Mustafa Imran Ali
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Citations
155
Test Set Compaction Algorithms for Com-Binational Circuits
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Test Volume and Application Time Reduction Through Scan Chain Concealment
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Test Data Compression Using Dictionaries with Selective Entries and Fixed-Length Indices
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Reducing Test Data Volume Using LFSR Reseeding with Seed Compression
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54
Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequencydirected Run-length (FDR) Codes
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An Efficient Test Vector Compression Scheme Using Selective Huffman Coding
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VariableLength Input Huffman Coding for System-on-a-Chip Test
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A Unified Approach to Reduce SOC Test Data Volume, Scan Power, and Testing Time
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Test Vector Encoding Using
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29
Using a Single Input to Support Multiple Scan Chains
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28
Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
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Multiscan-Based Test Compression and Hardware Decompression Using LZ77
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27
RL-Huffman Encoding for Test Compression and Power Reduction in Scan Application
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25
Packet-based Input Test Data Compression Techniques
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Nine-Coded Compression Technique for Testing Embedded Cores in SOCs
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Graph Coloring
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A Geometric-primitives-based Compression Scheme for Testing System-on-Chip
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23
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Extended Frequency-directed Run-length Codes with Improved Application to System-on-a-Chip Test Data Compres
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On reducing test data volume and test application time for multiple scan chain designs
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Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
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An optimal test compression procedure for combinational circuits
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16
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
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15
ATPG padding and ATE Vector repeat per port for Reducing Test Data Volume
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15
Broadcasting Test Patterns to Multiple Circuits
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15
Testing VLSI with Random Access Scan
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Test Set embedding for deterministic BIST Using a reconfigurable interconnection network
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14
Simultaneous Reduction in Volume of Test Data and Power Dissipation for System on-a-Chip
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13
Efficient BIST TPG Design and Test Set Compaction via Input Reduction
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Circularscan: A Scan Architecture for Test cost Reduction
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12
A reconfigurable Shared Scan-in Architecture
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11
Random Access Scan: A solution to Test Power, Test Data Volume and Test Time
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11
A Technique for High Ratio LZW Compression
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11
Design of Built-In Test Generator Circuits Using Width Compression
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11
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators
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11
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
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An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits
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10
A Random Access Scan Architecture to Reduce Hardware Overhead
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10
A Hybrid Coding strategy for optimized Test Data Compression
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9
A Novel Scan Architecture for PowerEfficient Rapid Test
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9
Progressive Random Access Scan: A Simultaneous Solution to Test Power, Test Data Volume and Test Time
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9
System-on-a-Chip Data Compression and Decompression Architecture Based on Golomb Codes
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7
Achieving high Encoding Efficiency with partial dynamic LFSR Reseeding
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6
BIST-Aided Scan Test-A New Method for Test Cost Reduction
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6
Test cost Reduction Through a reconfigurable Scan Architecture
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6
Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs
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6
Reducing the Number of Specified Values Per Test Vector by Increasing the Test Set Size
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Frugal Linear Network-based Test Decompression for Drastic Test Cost Reductions
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4
Fitting ATE Channels With Scan Chains: A Comparison Between a Test Data Compression Technique and Serial Loading of Scan Chains
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4
A Token Scan Architecture for Low Power Testing
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4
Cost-Effective Scan Architecture and a Test Application Scheme for Scan Testing with nonscan Power and Test Application cost. US Patent Application 20040153978
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4
A Cocktail Approach on Random Access Scan Toward Low Power and High Efficiency Test
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Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time
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4
Evolutionary Optimization in Code-Based Test Compression
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4
Test Compression for Scan Circuits Using Scan Polarity Adjustment and Pinpoint Test Relaxation
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4
Nozomu Togawa, Masao Yanagisawa, and Tatsuo Ohtsuki. Reducing Test Data Volume for Multiscan-based Designs Through Single Sequence Mixed Encoding
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4
Test Pattern Compression Using prelude vectors in fan-out Scan Chain with feedback Architecture
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4
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
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4
Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier
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3
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Test Vector Decomposition-Based Static Compaction Algorithms for Combinational Circuits
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A novel random access scan flip-flop design
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State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size
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3
Test Cost Reduction Using Partitioned Grid Random Access Scan
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3
Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding
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3
An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip
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3
An Efficient Test Vector Compression Technique Based on Block Merging
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3
Test Data Compression Based on inputoutput dependence
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3
Scan data volume reduction using periodically alterable MUXs decompressor
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A New Test Data Compression/Decompression Scheme to Reduce SOC Test Time
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The History and Future of Scan Design. EETimes Online
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Next Generation Scan Synthesis
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Tadahiro Ohmi. A Method for Compressing Test Data Based on Burrows-Wheeler Transformation
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Test Pattern Compression Saves Time and Bits. EE’05: Evaluation Engineering, pattern.asp
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Application of Arithmetic Coding to Compression
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2
Kohei Miyase, Seiji Kajihara, and Irith Pomeranz. On Test Data Volume Reduction for Multiple Scan Chain Designs
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2
MICRO: A New Hybrid Test Data Compression/Decompression Scheme
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Haruhiko Takase. Test Data Compression Technique Using Selective don’tcare Identification
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Masao Yanagisawa, and Tatsuo Ohtsuki. FCSCAN: An Efficient Multiscan-Based Test Compression Technique for Test Cost Reduction
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