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...f wire RC delays [7, 62], increasing power consumption [10, 69], and manufacturing challenges [36, 44, 76, 8]. The semiconductor industry has to overcome such challenges to keep pace with Moore’s law =-=[48]-=- and industry projections [36, 64]. Three-dimensional integration technology is a new technology that has the potential to address many of the challenges facing the semiconductor industry. 1.1.1 Worse...

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...the power density model by adding clock power and leakage power estimates to our highperformance processor. The Alpha processor has been reported to have the clock power to be 34% of the system power =-=[11]-=-. Since our baseline processor is based on the Alpha processor core, we assign the clock power to be 34% of the system power and correspondingly increase the power consumption of each of the functiona...

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...of the load and store queues, fully-associative TLBs, certain types of register renaming implementations [41, 72], and several other smaller buffers and queues (e.g., stream buffers and victim caches =-=[37]-=-). In the following discussion, we will use the dynamic instruction scheduler (also known as the issue queues or reservation stations) as an example of a typical CAM-based microarchitectural module. T...

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...stacked 3D IC will have approximately half (quarter) the footprint as the planar IC. 2.6.2 Experimental methodology We use a thermal simulation tool called HotSpot 3.0 from the University of Virginia =-=[67]-=- for thermal simulations. HotSpot can model multiple layers of silicon and metal required to model a 3D IC. HotSpot takes power consumption data and layer parameters as inputs and generates the steady...

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...components in a modern out-of-order processor require content addressable memories (CAMs) to perform fully-associative searches. These circuits are notorious for their poor scaling due to wire delays =-=[51]-=-, and addressing this problem for the dynamic instruction scheduler in particular has generated a large amount of research [24, 9, 46, 57, 12, 70, 28]. CAMs are also central to the implementation of t...

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... normally require an 8-read port, 4-write port register file. Instead, the designers chose to duplicate the entire contents of the register file such that each copy only needs half as many read ports =-=[39]-=-. Two full copies of a moderately ported register file proved to be smaller and faster than a single highly-ported structure. Since the register file is dominated by wire, 3D may provide an effective ...

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...echnology scaling has posed some new challenges to the semiconductor industry in this era of nanotechnology. Some of the technology challenges in the modern era include poor scaling of wire RC delays =-=[7, 62]-=-, increasing power consumption [10, 69], and manufacturing challenges [36, 44, 76, 8]. The semiconductor industry has to overcome such challenges to keep pace with Moore’s law [48] and industry projec...

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...tions based on parameters such as the number of entries, bit-width per entry, number and type of ports, and 2D vs. 3D organization. Our HSpice simulations use the Berkeley 70nm BSIM transistor models =-=[13]-=- and wire parameters extrapolated to 70nm from a TSMC 180nm technology. We sweep through a range of transistor sizings to minimize the latency of our register file configurations. We use a distributed...

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... in this era of nanotechnology. Some of the technology challenges in the modern era include poor scaling of wire RC delays [7, 62], increasing power consumption [10, 69], and manufacturing challenges =-=[36, 44, 76, 8]-=-. The semiconductor industry has to overcome such challenges to keep pace with Moore’s law [48] and industry projections [36, 64]. Three-dimensional integration technology is a new technology that has...

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...hallenges to the semiconductor industry in this era of nanotechnology. Some of the technology challenges in the modern era include poor scaling of wire RC delays [7, 62], increasing power consumption =-=[10, 69]-=-, and manufacturing challenges [36, 44, 76, 8]. The semiconductor industry has to overcome such challenges to keep pace with Moore’s law [48] and industry projections [36, 64]. Three-dimensional integ...

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...ay contribution becomes a significant component of the overall delay. Thus, the performance of many high-end microprocessors are increasingly limited not by transistor delay, but rather by wire delay =-=[26, 59, 7, 62]-=-. 1s1.1.2 Increasing Power Consumption Increased number of actively switching transistors, increased wiring complexity, and a higher frequency of operation together cause a significant increase in the...

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... power consumption [43] and large die area. An array multiplier may operate on either signed or unsigned numbers and may have a standard nonrecoded structure or a recoded one (using Booth’s algorithm =-=[6]-=- or a modified version of Booth’s algorithm [25]). An array multiplier typically has dense-logic as well as dense-wiring, thus making it an interesting design point for 3D implementation. Note that th...

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...mpanies are actively researching the technology [60, 5, 50, 29, 30]. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools =-=[16, 18, 22, 27, 54, 55, 58, 80]-=-. In this thesis, we study the microarchitectural impact of the 3D technology in the design of highperformance processors and quantify the benefits of 3D technology in building high-performance microp...

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.... These circuits are notorious for their poor scaling due to wire delays [51], and addressing this problem for the dynamic instruction scheduler in particular has generated a large amount of research =-=[24, 9, 46, 57, 12, 70, 28]-=-. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations [41, 72], and several other smaller buffers and q...

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.... These circuits are notorious for their poor scaling due to wire delays [51], and addressing this problem for the dynamic instruction scheduler in particular has generated a large amount of research =-=[24, 9, 46, 57, 12, 70, 28]-=-. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations [41, 72], and several other smaller buffers and q...

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...processor microarchitecture. Reducing the amount of wire can also have a significant impact on power consumption as interconnect power is already estimated to consume about one half of a chip’s power =-=[42]-=-. 3D technology provides an alternative means of increasing device density. Research is needed to study how processor designs can best exploit the benefits of 3D integration technology. 1.2 Scope of T...

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.... These circuits are notorious for their poor scaling due to wire delays [51], and addressing this problem for the dynamic instruction scheduler in particular has generated a large amount of research =-=[24, 9, 46, 57, 12, 70, 28]-=-. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations [41, 72], and several other smaller buffers and q...

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...tures. The maximum temperatures from our experiments is in contrast to the data published by prior research where the 2-die 3D ICs are reported to increase the on-chip temperatures by as much as 50 K =-=[17, 34]-=-. The large difference in the reported temperatures can be explained by the fact that we include modeling of vias, that serve as efficient heat dissipation paths and also that our model is built using...

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.... These circuits are notorious for their poor scaling due to wire delays [51], and addressing this problem for the dynamic instruction scheduler in particular has generated a large amount of research =-=[24, 9, 46, 57, 12, 70, 28]-=-. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations [41, 72], and several other smaller buffers and q...

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.... These circuits are notorious for their poor scaling due to wire delays [51], and addressing this problem for the dynamic instruction scheduler in particular has generated a large amount of research =-=[24, 9, 46, 57, 12, 70, 28]-=-. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations [41, 72], and several other smaller buffers and q...

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...mpanies are actively researching the technology [60, 5, 50, 29, 30]. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools =-=[16, 18, 22, 27, 54, 55, 58, 80]-=-. In this thesis, we study the microarchitectural impact of the 3D technology in the design of highperformance processors and quantify the benefits of 3D technology in building high-performance microp...

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...es. As a result, many microarchitecture-level proposals have been made to deal with the size, latency and power of the physical register file, including register caching [2] and register file banking =-=[77]-=-. While these techniques can reduce the average latency of register file access, they significantly complicate of the processor data and control paths. Increases in processor clock frequency and the r...

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...mpanies are actively researching the technology [60, 5, 50, 29, 30]. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools =-=[16, 18, 22, 27, 54, 55, 58, 80]-=-. In this thesis, we study the microarchitectural impact of the 3D technology in the design of highperformance processors and quantify the benefits of 3D technology in building high-performance microp...

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...mpanies are actively researching the technology [60, 5, 50, 29, 30]. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools =-=[16, 18, 22, 27, 54, 55, 58, 80]-=-. In this thesis, we study the microarchitectural impact of the 3D technology in the design of highperformance processors and quantify the benefits of 3D technology in building high-performance microp...

Citation Context

...hallenges to the semiconductor industry in this era of nanotechnology. Some of the technology challenges in the modern era include poor scaling of wire RC delays [7, 62], increasing power consumption =-=[10, 69]-=-, and manufacturing challenges [36, 44, 76, 8]. The semiconductor industry has to overcome such challenges to keep pace with Moore’s law [48] and industry projections [36, 64]. Three-dimensional integ...

Citation Context

...mpanies are actively researching the technology [60, 5, 50, 29, 30]. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools =-=[16, 18, 22, 27, 54, 55, 58, 80]-=-. In this thesis, we study the microarchitectural impact of the 3D technology in the design of highperformance processors and quantify the benefits of 3D technology in building high-performance microp...

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.... These circuits are notorious for their poor scaling due to wire delays [51], and addressing this problem for the dynamic instruction scheduler in particular has generated a large amount of research =-=[24, 9, 46, 57, 12, 70, 28]-=-. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations [41, 72], and several other smaller buffers and q...

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...tructions per second (IPC) rates. As a result, many microarchitecture-level proposals have been made to deal with the size, latency and power of the physical register file, including register caching =-=[2]-=- and register file banking [77]. While these techniques can reduce the average latency of register file access, they significantly complicate of the processor data and control paths. Increases in proc...

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... the ability to place and route in the third dimension provide new opportunities for microarchitecture design. General purpose and embedded processor companies are actively researching the technology =-=[60, 5, 50, 29, 30]-=-. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools [16, 18, 22, 27, 54, 55, 58, 80]. In this thesis, we study the micr...

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...rchitectures, the physical register file also contains the instruction status information required for maintaining in-order retirement of instructions; each of our registers contains 160 bits of data =-=[66]-=-. We simulate a 128-entry register file which is representative of modern processors as well as a 256-entry version to model future register file demands. The 3D implementations of the physical regist...

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... in this era of nanotechnology. Some of the technology challenges in the modern era include poor scaling of wire RC delays [7, 62], increasing power consumption [10, 69], and manufacturing challenges =-=[36, 44, 76, 8]-=-. The semiconductor industry has to overcome such challenges to keep pace with Moore’s law [48] and industry projections [36, 64]. Three-dimensional integration technology is a new technology that has...

Citation Context

...array multiplier may operate on either signed or unsigned numbers and may have a standard nonrecoded structure or a recoded one (using Booth’s algorithm [6] or a modified version of Booth’s algorithm =-=[25]-=-). An array multiplier typically has dense-logic as well as dense-wiring, thus making it an interesting design point for 3D implementation. Note that the dense-logic, dense-wire characteristics of the...

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...der superscalar nature of the processors, but new issues such as relative wire delay, power consumption and thermal reliability have become significant challenges due to continuous technology scaling =-=[80, 51, 7, 33, 42, 69]-=-. p3 The new challenges of design complexity, wire delay, power density issues, and thermal issues have lead to multiple design parameters or constraints in addition to performance. Due to the number ...

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...tures. The maximum temperatures from our experiments is in contrast to the data published by prior research where the 2-die 3D ICs are reported to increase the on-chip temperatures by as much as 50 K =-=[17, 34]-=-. The large difference in the reported temperatures can be explained by the fact that we include modeling of vias, that serve as efficient heat dissipation paths and also that our model is built using...

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...ay contribution becomes a significant component of the overall delay. Thus, the performance of many high-end microprocessors are increasingly limited not by transistor delay, but rather by wire delay =-=[26, 59, 7, 62]-=-. 1s1.1.2 Increasing Power Consumption Increased number of actively switching transistors, increased wiring complexity, and a higher frequency of operation together cause a significant increase in the...

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...power consumption of each of the functional blocks in both the planar and the 3D ICs. We model the leakage power to be 15% of the system power in a 70 nm technology based on the leakage power data in =-=[65]-=-. Note that we do not model the dependence of leakage power on temperature. Figure 27 plots the increase over the planar IC temperature for the 3D ICs after taking the system clock power and the leaka...

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... the ability to place and route in the third dimension provide new opportunities for microarchitecture design. General purpose and embedded processor companies are actively researching the technology =-=[60, 5, 50, 29, 30]-=-. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools [16, 18, 22, 27, 54, 55, 58, 80]. In this thesis, we study the micr...

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.... These circuits are notorious for their poor scaling due to wire delays [51], and addressing this problem for the dynamic instruction scheduler in particular has generated a large amount of research =-=[24, 9, 46, 57, 12, 70, 28]-=-. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations [41, 72], and several other smaller buffers and q...

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...ge amount of research [24, 9, 46, 57, 12, 70, 28]. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations =-=[41, 72]-=-, and several other smaller buffers and queues (e.g., stream buffers and victim caches [37]). In the following discussion, we will use the dynamic instruction scheduler (also known as the issue queues...

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... different types of 3D integration technologies based on the styles of fabrication. A majority of the 3D technologies fall under one of the two categories, namely Multi-layer Buried Structures (MLBS) =-=[75]-=- and Die-Bonding 3D technology. MLBS 3D technology fabricates successive stacked layers of active devices interconnected by a top level metal interface. The die-bonding 3D technology processes the cir...

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... the logic-dominated adder circuit and wire-dominated shifter circuit. Thus, the underlying benefits and trade-offs might be different for the array multiplier than the adder and the shifter circuits =-=[56]-=-. a3 a2 a1 a0 x3 x2 x1 x0 a3x0 a2x0 a1x0 a0x0 a3x1 a2x1 a1x1 a0x1 a3x2 a2x2 a1x2 a0x2 a3x3 a2x3 a1x3 a0x3 p7 p6 p5 p4 p3 p2 p1 p0 Table 12: A 4-bit multiplication procedure 53sp7 a3x3 p6 a3x2 p5 a3x1 ...

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...ink and experience a longer heat dissipation path in the vertical direction to the heat sink. Increased power density has made thermal management to be identified as a critical issue in 3D technology =-=[21]-=-. In this section, we analyze the thermal impact of 3D IC technology on high-performance microprocessors by estimating the temperatures of a planar IC based on the Alpha 21364 processor as well as 2-d...

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... a multiply-accumulate operation with instruction set extensions such as Intel MMX [35]. The most common multiplier architectures used in high-speed datapaths belong to the class of array multipliers =-=[1, 43]-=-. Some of the challenges of the array multipliers are their high power consumption [43] and large die area. An array multiplier may operate on either signed or unsigned numbers and may have a standard...

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... the ability to place and route in the third dimension provide new opportunities for microarchitecture design. General purpose and embedded processor companies are actively researching the technology =-=[60, 5, 50, 29, 30]-=-. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools [16, 18, 22, 27, 54, 55, 58, 80]. In this thesis, we study the micr...

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... a multiply-accumulate operation with instruction set extensions such as Intel MMX [35]. The most common multiplier architectures used in high-speed datapaths belong to the class of array multipliers =-=[1, 43]-=-. Some of the challenges of the array multipliers are their high power consumption [43] and large die area. An array multiplier may operate on either signed or unsigned numbers and may have a standard...

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...ge amount of research [24, 9, 46, 57, 12, 70, 28]. CAMs are also central to the implementation of the load and store queues, fully-associative TLBs, certain types of register renaming implementations =-=[41, 72]-=-, and several other smaller buffers and queues (e.g., stream buffers and victim caches [37]). In the following discussion, we will use the dynamic instruction scheduler (also known as the issue queues...

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...stance and capacitance. Random dopant fluctuations and poly line-edge-roughness cause threshold voltage variations. 1.1.4 Three-dimensional Integration Technology 3-Dimensional integration technology =-=[38]-=- is an emergent technology that greatly reduces the impact of wire RC delays by placing the active devices in vertical stacked layers and providing vertical connectivity. Two functional units connecte...

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... 3D Processor In the design of complex systems such as processors, evaluating trade-offs among a large number of design parameters is very important in order to come up with the optimal configuration =-=[78]-=- since there are no proven analytic procedures for computing the optimal design parameters of a microprocessor. In the traditional processor design process, the processor microarchitecture is determin...

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...ready less than the wavelength of the light used for photolithography. Advances in optics and moving to shorter wavelength radiation such as EUV may provide a few more doublings of transistor density =-=[4]-=-. Process variations are becoming increasingly nondeterministic in current and future technology generations. Process variations increase the variance of the circuit delays from their expected (mean) ...

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...mpanies are actively researching the technology [60, 5, 50, 29, 30]. Academic research effort has focused on the circuit implementation, process technology, physical design and automated design tools =-=[16, 18, 22, 27, 54, 55, 58, 80]-=-. In this thesis, we study the microarchitectural impact of the 3D technology in the design of highperformance processors and quantify the benefits of 3D technology in building high-performance microp...

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...f a read operation and the power consumption of the entire array. We model the die-to-die interconnect as 10µm of top-level metal plus the corresponding via contact resistance based on published data =-=[71, 61, 23]-=-. To optimize our cache designs, we sweep through a range of transistor sizings as well as bank organizations. We use the configurations that minimize overall cache access time. We simulate a cache re...

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...may affect yield because an n-die stack can be rendered inoperational by a single bad die, even if the other n − 1 are fine. The increased power density may require more aggressive cooling mechanisms =-=[53]-=-, also adding cost. A full analysis of the economic viability of 3D fabrication is beyond the scope of this thesis. An open research question is in determining the benefit that can be extracted from t...

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...st travel 5µm to cross between the two die faces and 20µm to cross the B2B interface. These distances are conservative since currently available 3D technologies already thin the die down to only 12µm =-=[74]-=-. Using this methodology, we design planar, two-die 3D and four-die 3D implementations of the primary processor modules. This includes the issue queues (Int, FP, Load, Store), RATs, register files, ca...

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...ach of the individual die. Advances in 2D and 3D fabrication complement each other. Therefore, 3D can reap the benefits of any advances in traditional planar processes such as double-gate transistors =-=[68]-=-, tri-gate transistors [15], finFETs [31], strained silicon [47], metal gates [14] and other technologies. An intuitive application of 3D integration is the stacking of a very large last-level cache, ...

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.... Therefore, 3D can reap the benefits of any advances in traditional planar processes such as double-gate transistors [68], tri-gate transistors [15], finFETs [31], strained silicon [47], metal gates =-=[14]-=- and other technologies. An intuitive application of 3D integration is the stacking of a very large last-level cache, e.g., L3 cache, on top of a traditional execution core of the processor. Figure 3(...

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...ing multiple objectives to suggest “Paretooptimal” designs. Pareto optimality has been described as the “best that could be achieved with all objectives without disadvantaging at least one objective” =-=[79]-=-. I will compare the performances of a set of architectures by constraining a few of the objectives such as performance and via area and exploring other objectives such as power and energy. I propose ...