A great interest has been gained in recent years by a new error-correcting code technique, known as "turbo coding," which has been proven to offer performance closer to the Shannon's limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and performance; the impact on the VLSI complexity of system parameters like the state number, number of iterations, and code rate are evaluated for the different solutions. The results of this architectural study have then been exploited for the design of a specific decoder, implementing a serial concatenation scheme with 2/3 and 3/4 codes; the designed circuit occupies 35 mm , supports a 2-Mb/s data rate, and for a bit error probability of 10 06 , yields a coding gain larger than 7 dB, with ten iterations.

This is a tutorial paper meant to introduce the reader to the new concept of turbo codes. This is a new and very powerful error correction technique which outperforms all previous known coding schemes. It can be used in any communication system where a significant power saving is required or the operating signal--to--noise ratio (SNR) is very low. Deep space communications, mobile satellite/cellular communications, microwave links, paging, etc., are some of the possible applications of this revolutionary coding technique. Part I of the paper discussed the history of turbo codes, why they are different from traditional convolutional/block codes, the turbo encoder structures and issues related to the interleaver design. Part II addresses the decoder architecture, the achievable performance for turbo codes for a wide range of coding rates and modulation techniques and discusses delay and implementation issues. 2 1 Introduction The optimum decoding of turbo codes is the maximum likeli...

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Previously [1], it has been shown that parallel concatenated convolutional codes (PCCCs) can be modeled as a special case of serial concatenated convolutional codes (SCCCs). In this paper, we focus on this relationship with a goal of providing a parent code design that generates PCCC, SCCC and a family of hybrid code performances that bridge the gap between the two. The proposed code is very flexible since a single encoder can produce the entire range of outputs while possessing the same decoder structure to retrieve the input data. Simulation results of the error rate performance of these codes vs. signal to noise ratio are plotted. Finally, an insight into design and analysis of good parent codes is provided.

Abstract—We consider the application of concatenated codes with interleaver and iterative decoding to optical communication systems. We show how to obtain the optimum log-likelihood ratio to be provided to the soft decoder in the optical channel environment, and compare the performance of a decoder using it with the one employing a Gaussian approximation of the optical channel. Sim-ulation results refer to practical turbo-product codes, and encom-pass the effect of quantization on the log-likelihood ratio. The re-sults show that the Gaussian assumption in computing the log-like-lihood ratio for the optical channel leads to significant losses. Index Terms—Modeling, optical communication, product codes, soft-decision decoding. I.

Abstract — For many digital communication system bandwidth and transmission power are limited resource and it is well known that the use of recursive convolution encoder (RCE) plays a fundamental role to increasing power and spectrum efficiency. The development of error correction technique with increasing coding gain has a limit, arising from the channel capacity. Convolution code is channel code, which extensively used in communication system. The paper describes in three phases of Recursive convolution Encoder. System level design as first phase, containing trellis diagram and state table RTL vie of recursive convolution encoder also explains timing waveform and parameter require for developing the convolution encoder. Circuit level design using MOS transistor as second phase and then Layout or Physical design of recursive convolution encoder as third phase and finally explain the application and conclusion I.

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