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63
Accurate reliablity evaluation and enhancement via probabilistic transfer matrices
 In Proc
, 2005
"... Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs). In particular, we apply them to evaluate circuit reliability in the presence of s ..."
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Cited by 43 (5 self)
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Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs). In particular, we apply them to evaluate circuit reliability in the presence of soft errors, which involves combining the PTMs of gates to form an overall circuit PTM. Information such as output probabilities, the overall probability of error, and signal observability can then be extracted from the circuit PTM. We employ algebraic decision diagrams (ADDs) to improve the efficiency of PTM operations. A particularly challenging technical problem, solved in our work, is to simultaneously extend tensor products and matrix multiplication in terms of ADDs to nonsquare matrices. Our PTMbased method enables accurate evaluation of reliability for moderately large circuits and can be extended by circuit partitioning. To demonstrate the power of the PTM approach, we apply it to several problems in faulttolerant design and reliability improvement. 1
Probabilistic model checking in practice: Case sudies with PRISM
"... In this paper, we describe some practical applications of probabilistic model checking, a technique for the formal analysis of systems which exhibit stochastic behaviour. We give an overview of a selection of case studies carried out using the probabilistic model checking tool PRISM, demonstrating ..."
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Cited by 31 (9 self)
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In this paper, we describe some practical applications of probabilistic model checking, a technique for the formal analysis of systems which exhibit stochastic behaviour. We give an overview of a selection of case studies carried out using the probabilistic model checking tool PRISM, demonstrating the wide range of application domains to which these methods are applicable. We also illustrate several benefits of using formal verification techniques to analyse probabilistic systems, including: (i) that they allow a wide range of numerical properties to be computed accurately; and (ii) that they perform a complete and exhaustive analysis enabling, for example, a study of best and worstcase scenarios.
A probabilisticbased design methodology for nanoscale computation
 in Proc. Int. Conf. Comput.Aided Des
"... As current siliconbased techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates ..."
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Cited by 21 (4 self)
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As current siliconbased techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this paper, we propose a probabilisticbased design methodology for designing nanoscale computer architectures based on Markov Random Fields (MRF). The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures based on the belief propagation algorithm. Belief propagation is a way of organizing the global computation of marginal belief in terms of smaller local computations. We will illustrate the proposed design methodology with some elementary logic examples. Figure 1: The principle of switching with carbon nanotubes. Tubes are joined by an attractive electric field. Molecular forces maintain the connection when the field is removed. (After Lieber [11]). 1.
Evaluating the reliability of defecttolerant architectures for nanotechnology with probabilistic model checking
 In Proc. International Conference on VLSI Design (VSLI’04
, 2004
"... As we move from deep submicron technology to nanotechnology for device manufacture, the need for defecttolerant architectures is gaining importance. This is because, at the nanoscale, devices will be prone to errors due to manufacturing defects, ageing, and transient faults. Microarchitects will b ..."
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Cited by 21 (6 self)
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As we move from deep submicron technology to nanotechnology for device manufacture, the need for defecttolerant architectures is gaining importance. This is because, at the nanoscale, devices will be prone to errors due to manufacturing defects, ageing, and transient faults. Microarchitects will be required to design their logic around defect tolerance through redundancy. However, measures of reliability must be quantified in order for such design methodologies to be acceptable. We propose a CAD framework based on probabilistic model checking which provides efficient evaluation of the reliability/redundancy tradeoff for defecttolerant architectures. This framework can model probabilistic assumptions about defects, easily compute reliability figures and help designers make the right decisions. We demonstrate the power of our framework by evaluating the reliability/redundancy tradeoff of a canonical example, namely NAND multiplexing. We not only find errors in analytically computed bounds published recently, but we also show how to use our framework to evaluate various facets of design tradeoff for reliability. 1.
NANOPRISM: a tool for evaluating granularity vs. reliability tradeoffs in nano architectures
 in Proc. Great Lakes Symp. VLSI
, 2004
"... It is expected that nanoscale devices and interconnections will introduce unprecedented level of defects, noise and interferences in the substrates. This consideration motivates the search for new architectural paradigms based on redundancy based defecttolerant designs. However, redundancy is not ..."
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Cited by 17 (7 self)
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It is expected that nanoscale devices and interconnections will introduce unprecedented level of defects, noise and interferences in the substrates. This consideration motivates the search for new architectural paradigms based on redundancy based defecttolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause lack of reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve optimal reliability. Various forms of redundancy such as NAND multiplexing, Triple Modular Redundancy (TMR), Cascaded Triple Modular Redundancy (CTMR) have been considered in the faulttolerance literature. Also, redundancy has been applied at different levels of granularity, such as gate level, logic block level, logic function level, unit level etc. The questions we try to answer in this paper is what level of granularity and what redundancy levels result in optimal reliability for specific architectures. In this paper, we extend previous work on evaluating reliabilityredundancy tradeoffs for NAND multiplexing to granularity vs. redundancy vs. reliability tradeoffs for other redundancy mechanisms, and present our automation mechanism using the probabilistic model checking tool PRISM. We illustrate the power of this automation by pointing out certain anomalies of these tradeoffs which are counter intuitive and can only be obtained by designers through automation, thereby providing better insight into defecttolerant design decisions.
Stochastic computational models for accurate reliability evaluation of logic circuits
 in Proc. Great Lakes Symposium on VLSI
, 2010
"... As reliability becomes a major concern with the continuous scaling of CMOS technology, several computational methodologies have been developed for the reliability evaluation of logic circuits. Previous accurate analytical approaches, however, have a computational complexity that generally increases ..."
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Cited by 14 (7 self)
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As reliability becomes a major concern with the continuous scaling of CMOS technology, several computational methodologies have been developed for the reliability evaluation of logic circuits. Previous accurate analytical approaches, however, have a computational complexity that generally increases exponentially with the size of a circuit, making the evaluation of large circuits intractable. This paper presents novel computational models based on stochastic computation, in which probabilities are encoded in the statistics of random binary bit streams, for the reliability evaluation of logic circuits. A computational approach using the stochastic computational models (SCMs) accurately determines the reliability of a circuit with its precision only limited by the random fluctuations inherent in the representation of random binary bit streams. The SCM approach has a linear computational complexity and is therefore scalable for use for any large circuits. Our simulation results demonstrate the accuracy and scalability of the SCM approach, and suggest its possible applications in VLSI design.
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
 ACM Transactions on Design Automation of Electronic Systems
"... We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are wellsuited to reliability and error susceptibility calculations. A few simple composition rules based o ..."
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Cited by 13 (2 self)
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We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are wellsuited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate variables and eliminate redundant variables, which aid in the numerical computation of circuit PTMs. We use PTMs to evaluate circuit reliability and derive polynomial approximations for circuit error probabilities in terms of gate error probabilities. PTMs can also analyze the effects of logic and electrical masking on error mitigation. We show that ignoring logic masking can overestimate errors by an order of magnitude. We incorporate electrical masking by computing error attenuation probabilities, based on analytical models, into an extended PTM
Evaluating the reliability of NAND multiplexing with PRISM
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2005
"... Probabilistic model checking is a formal verification technique for analysing the reliability and performance of systems exhibiting stochastic behaviour. In this paper, we demonstrate the applicability of this approach and, in particular, the probabilistic model checking tool PRISM to the evaluati ..."
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Cited by 13 (4 self)
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Probabilistic model checking is a formal verification technique for analysing the reliability and performance of systems exhibiting stochastic behaviour. In this paper, we demonstrate the applicability of this approach and, in particular, the probabilistic model checking tool PRISM to the evaluation of reliability and redundancy of defecttolerant systems in the field of computeraided design. We illustrate the technique with an example due to von Neumann, namely NAND multiplexing. We show how, having constructed a model of a defecttolerant system incorporating probabilistic assumptions about its defects, it is straightforward to compute a range of reliability measures and investigate how they are affected by slight variations in the behaviour of the system. This allows a designer to evaluate, for example, the tradeoff between redundancy and reliability in the design. We also highlight errors in analytically computed reliability bounds, recently published for the same case study.
The Future of Integrated Circuits: A Survey of Nanoelectronics”, online at http://www.ee.washington. edu/faculty/hauck/publications/NanoSurvey.pdf. A. Bachtold et al., “Logic Circuits with Carbon Nanotube
 Transistors”, Science
, 2001
"... While most of the electronics industry is dependent on the everdecreasing size of lithographic transistors, this scaling cannot continue indefinitely. Nanoelectronics (circuits built with components on the scale of 10nm) seem to be the most promising successor to lithographic based ICs. Molecular ..."
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Cited by 10 (0 self)
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While most of the electronics industry is dependent on the everdecreasing size of lithographic transistors, this scaling cannot continue indefinitely. Nanoelectronics (circuits built with components on the scale of 10nm) seem to be the most promising successor to lithographic based ICs. Molecular scale devices including diodes, bistable switches, carbon nanotubes, and nanowires have been fabricated and characterized in chemistry labs. Techniques for selfassembling these devices into different architectures have also been demonstrated and used to build small scale prototypes. While these devices and assembly techniques will lead to nanoscale electronics, they also have the drawback of being prone to defects and transient faults. Fault tolerance techniques will be crucial to the use of nanoelectronics. Finally, changes to the software tools that support the fabrication and use of ICs will be needed to extend them to support nanoelectronics. This survey introduces nanoelectronics and reviews the current progress made in research in the areas of technologies, architectures, fault tolerance, and software tools. 1.
Bifurcations and fundamental error bounds for faulttolerant Computations
 IEEE Tr. Nanotechnology
"... Abstract—In the emerging nanotechnologies, faulty components may be an integral part of a system. For the system to be reliable, the error of the building blocks has to be smaller than a threshold. Therefore, finding exact error thresholds for noisy gates is one of the most challenging problems in f ..."
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Cited by 10 (2 self)
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Abstract—In the emerging nanotechnologies, faulty components may be an integral part of a system. For the system to be reliable, the error of the building blocks has to be smaller than a threshold. Therefore, finding exact error thresholds for noisy gates is one of the most challenging problems in faulttolerant computations. Under the von Neumann’s probabilistic computing framework, we show that computation by circuits built out of noisy NAND gates with an arbitrary number of inputs under worst case operation can be readily described by nonlinear discrete maps. Bifurcation analysis of such maps naturally gives the exact error thresholds above which no reliable computation is possible. It is further shown that the maximum threshold value for ainput NAND gate is obtained when =5. This implies that if one chooses NAND gate as basic building blocks, then the optimal number of inputs for the NAND gate may be very different from the conventional value of 2. The analysis technique generalizes to other types of gates and circuits that use voting to improve reliability, as well as a network built out of the socalled pararestituted NAND gates recently proposed by Sadek et al. Nonlinear dynamics theory offers an interesting perspective to study rich nonlinear interactions among faulty components and design nanoscale faulttolerant architectures. Index Terms—Bifurcation, error threshold, noisy NAND gate, probabilistic/reliable computation. I.