A factor graph is a bipartite graph that expresses how a "global" function of many variables factors into a product of "local" functions. Factor graphs subsume many other graphical models including Bayesian networks, Markov random fields, and Tanner graphs. Following one simple computational rule, the sum-product algorithm operates in factor graphs to compute---either exactly or approximately---various marginal functions by distributed message-passing in the graph. A wide variety of algorithms developed in artificial intelligence, signal processing, and digital communications can be derived as specific instances of the sum-product algorithm, including the forward/backward algorithm, the Viterbi algorithm, the iterative "turbo" decoding algorithm, Pearl's belief propagation algorithm for Bayesian networks, the Kalman filter, and certain fast Fourier transform algorithms.

Today's communications systems especially in the field of wireless communications rely on many different algorithms to provide applications with constantly increasing data rates and higher quality. This development combined with the wireless channel characteristics as well as the invention of turbo codes has particularly increased the importance of interleaver algorithms. In this paper we demonstrate the feasibility to exploit the hardware parallelism in order to accelerate the interleaving procedure. Based on a heuristic algorithm the possible speedup for different interleavers as a function of the degree of parallelism of the hardware is presented. The parallelization is generic in the sense that the assumed underlying hardware is based on a parallel datapath DSP architecture and therefore provides the flexibility of software solutions.

A multiple access system is developed in this paper by means of Linear Periodic Time Varying (LPTV) filters. We construct an LPTV-based Multiple Access (LPTVMA) system with complex modulators and matrix interleavers. This LPTVMA system has good spreading properties and small Multi User Interference (MUI). However, the equalization problem of such LPTV filters in stationary multipath channels remains unsolved. We show that, due to the presence of matrix interleavers, the received signal is affected by a time varying delay. By using a Zero Padding (ZP) technique, classical single user equalization techniques can be used. Further, when the users in the LPTVMA system are quasi-synchronous, MUI-free transceivers can be achieved. Comparisons of the LPTVMA system with a Chip Interleaved Block Spread (CIBS)- CDMA system are made in quasi-synchronous and asynchronous scenarios. Simulations showed that the LPTVMA system has better performances in the asynchronous scenario than the CIBS-CDMA system. 1.

[11] D. Chase, “A class of algorithms for decoding block codes with channel measurement information, ” IEEE Trans. Inform. Theory, vol. IT-18, pp.

A mathematical characterization of serially-pruned permutations (SPPs) employed in variable-length permuters and their associated fast pruning algorithms and architectures are proposed. Permuters are used in many signal processing systems for shuffling data and in communication systems as an adjunct to coding for error correction. Typically only a small set of discrete permuter lengths are supported. Serial pruning is a simple technique to alter the length of a permutation to support a wider range of lengths, but results in a serial processing bottleneck. In this paper, parallelizing SPPs is formulated in terms of recursively computing sums involving integer floor and related functions using integer operations, in a fashion analogous to evaluating Dedekind sums. A mathematical treatment for bit-reversal permutations (BRPs) is presented, and closed-form expressions for BRP statistics including descents/ascents, major index, excedances/descedances, inversions, and serial correlations are derived. It is shown that BRP sequences have weak correlation properties. Moreover, a new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers is proposed. Using this statistic, a recursive algorithm that computes the minimum inliers count of a pruned BR interleaver (PBRI) in logarithmic time complexity is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers, as well as applications to pruned fast Fourier transforms and LTE turbo interleavers, are also presented. Moreover, hardware-efficient architectures for the proposed algorithms are developed. Simulation results of interleavers employed in modern communication standards demonstrate 3 to 4 orders of magnitude improvement in interleaving time compared to existing approaches.

Improved closed-form bounds on the performance of convolutional codes with correlated Rayleigh fading

Abstract. For pi ∈ Sn, let d(pi) be the arithmetic average of {|i − pi(i)|; 1 ≤ i ≤ n}. Then 0 ≤ d(pi)/n ≤ 1/2, the expected value of d(pi)/n approaches 1/3 as n approaches infinity, and most permutations have d(pi)/n close to 1/3. We also describe all permutations with d(pi)/n = 1/2. Let s+(pi) and s∗(pi) be the arithmetic and geometric averages of {|pi(i) − pi(i + 1)|; 1 ≤ i < n}, respectively. Let M+, M ∗ be the maxima of s+ and s ∗ over Sn, respectively. Then M+ = (2m2 − 1)/(2m − 1) when n = 2m, M+ = (2m2 + 2m − 1)/(2m) when n = 2m + 1, M ∗ = (mm(m + 1)m−1)1/(n−1) when n = 2m, and M ∗ = (mm(m + 1)(m + 2)m−1)1/(n−1) when n = 2m + 1> 1. We also describe all permutations pi, σ with s+(pi) =M+, s∗(σ) =M∗. 1. Motivation and