Results 1 
6 of
6
IMITATOR: A tool for synthesizing constraints on timing bounds of timed automata
 In Proc. ICTAC’09, volume 5684 of LNCS
, 2009
"... Abstract. We present here Imitator, a tool for synthesizing constraints on timing bounds (seen as parameters) in the framework of timed automata. Unlike classical synthesis methods, we take advantage of a given reference valuation of the parameters for which the system is known to behave properly. O ..."
Abstract

Cited by 9 (5 self)
 Add to MetaCart
(Show Context)
Abstract. We present here Imitator, a tool for synthesizing constraints on timing bounds (seen as parameters) in the framework of timed automata. Unlike classical synthesis methods, we take advantage of a given reference valuation of the parameters for which the system is known to behave properly. Our aim is to generate a constraint such that, under any valuation satisfying this constraint, the system is guaranteed to behave, in terms of alternating sequences of locations and actions, as under the reference valuation. This is useful for safely relaxing some values of the reference valuation, and optimizing timing bounds of the system. We have successfully applied our tool to various examples of asynchronous circuits and protocols. 1
Synthesizing Parametric Constraints on Various Case Studies Using IMITATOR (Preliminary Version)
"... We consider in this report systems modeled by timed automata. The timing bounds involved in the action guards and location invariants of our timed automata are not constants, but parameters. Those parametric timed automata allow to model various kinds of timed systems, e.g. communication protocols ..."
Abstract

Cited by 4 (4 self)
 Add to MetaCart
(Show Context)
We consider in this report systems modeled by timed automata. The timing bounds involved in the action guards and location invariants of our timed automata are not constants, but parameters. Those parametric timed automata allow to model various kinds of timed systems, e.g. communication protocols
Time Separation of Events: An Inverse Method
, 2007
"... Abstract. The problem of “time separation ” can be stated as follows: Given a system made of several connected components, each one entailing a local delay known with uncertainty, what is the maximum time for traversing the global system? This problem is useful, e.g. in the domain of digital circuit ..."
Abstract

Cited by 3 (3 self)
 Add to MetaCart
(Show Context)
Abstract. The problem of “time separation ” can be stated as follows: Given a system made of several connected components, each one entailing a local delay known with uncertainty, what is the maximum time for traversing the global system? This problem is useful, e.g. in the domain of digital circuits, for determining the global traversal time of a signal from the knowledge of bounds on the component propagation delays. The uncertainty on each component delay is given under the form of an interval. The general problem is NPcomplete. We focus here on the inverse problem: we seek a set of intervals for the component delays for which the global traversal time is guaranteed to be no greater than a specified maximum. We give a polynomial time method to solve it. As a typical application, we show how to use the method in order to relax some specified local delays while preserving the maximum traversal time. This is especially useful, in the area of digital circuits, for optimizing “setup” timings of input signals (minimum timings required for stability). 1
Formal Timing Analysis of FullCustom Memory Circuits
"... Abstract — Embedded SRAM are key bricks for system on chip performances. The competition is keen for IP providers. Thus, the timing margins must be reduced in order to release extra performances to the customers. Today, the verification is mainly based on spice simulations which are very accurate, b ..."
Abstract
 Add to MetaCart
(Show Context)
Abstract — Embedded SRAM are key bricks for system on chip performances. The competition is keen for IP providers. Thus, the timing margins must be reduced in order to release extra performances to the customers. Today, the verification is mainly based on spice simulations which are very accurate, but very slow and with a limited coverage. Our strategy is then to combine transistor abstraction with timings and parametric formal verification techniques. We illustrate our methodology on a portion of a commercial embedded memory and show how it can be used to improve the product datasheet. Moreover, the automated generation of the design constraint equations is an innovative approach to help designers with performances improvement. I.
Task T4 Livrables D4.2 and D4.3 established at T0 + 48 Experiments of Prototype Tools on Case Studies, Comparison of obtained results and Conclusion
"... This document is a merge of livrables D4.2 ”Experiments of Prototype Tools on Cases Studies ” and D4.3 ”Comparison of obtained results and Conclusion ” in the initial proposition. It concludes the VALMEM project by applying the set of tools developed during the project to (some of) the case studies ..."
Abstract
 Add to MetaCart
(Show Context)
This document is a merge of livrables D4.2 ”Experiments of Prototype Tools on Cases Studies ” and D4.3 ”Comparison of obtained results and Conclusion ” in the initial proposition. It concludes the VALMEM project by applying the set of tools developed during the project to (some of) the case studies defined initially. The obtained results are discussed and compared with standard methodologies outcomes. In the initial proposition, these two documents were separated since we planned to apply our flow to several case studies (SPSMALL memory, SPREG memory, including selftimed logics). At the end of the project, we were able to apply it to the SPSMALL memory, but the particular mechanisms of SPREG have not been introduced into the preliminary stages of our flow. Hence we found preferable to merge the two documents into a unique one. This document is structured as follows: the first part recalls our methodological flow. Parts 2 to 6 describe the application of this flow to SPSMALL memory. The architecture and specificities of SPSMALL are recalled in section 2; abstraction and timing extraction are applied in section 3; formal analysis performed by timedmodel checking and parametric timed modelchecking are reported into sections 4 and 5. Encountered and remaining difficulties are commented in section 6. Comparisons and conclusions are drawn in section 7. 1 Analysis Flow of full custom memory proposed in the VALMEM project The Functional and Timing analysis problem we concentrate on can be expressed in the following way. Given: – a fullcustom memory circuit described at transistor level, for a given technology, – a specification provided by the manufacturer, describing (1) the conditions to be met by the environment (called nominal conditions), (2) the guaranteed performances of the memory (namely the access timings) assuming these nominal conditions are met. Determine: – the correctness of the access timings given in the specification, – the extremal stability periods of environment signals still guarantying the functionality and the access timings of the memory.