Results 1 - 10
of
14
A current-mode conductance-based silicon neuron for address-event neuromorphic systems
- In Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
"... neuromorphic systems ..."
(Show Context)
Silicon Neurons that Compute
"... Abstract. We use neuromorphic chips to perform arbitrary mathematical computations for the first time. Static and dynamic computations are realized with heterogeneous spiking silicon neurons by programming their weighted connections. Using 4K neurons with 16M feed-forward or recurrent synaptic conne ..."
Abstract
-
Cited by 8 (2 self)
- Add to MetaCart
(Show Context)
Abstract. We use neuromorphic chips to perform arbitrary mathematical computations for the first time. Static and dynamic computations are realized with heterogeneous spiking silicon neurons by programming their weighted connections. Using 4K neurons with 16M feed-forward or recurrent synaptic connections, formed by 256K local arbors, we communicate a scalar stimulus, quadratically transform its value, and compute its time integral. Our approach provides a promising alternative for extremely power-constrained embedded controllers, such as fully implantable neuroprosthetic decoders.
Nonlinear Influence of T-Channels in an in silico Relay Neuron
"... Abstract—Thalamic relay cells express distinctive response modes based on the state of a low-threshold calcium channel (T-channel). When the channel is fully active (burst mode), the cell responds to inputs with a high-frequency burst of spikes; with the channel inactive (tonic mode), the cell respo ..."
Abstract
-
Cited by 2 (0 self)
- Add to MetaCart
(Show Context)
Abstract—Thalamic relay cells express distinctive response modes based on the state of a low-threshold calcium channel (T-channel). When the channel is fully active (burst mode), the cell responds to inputs with a high-frequency burst of spikes; with the channel inactive (tonic mode), the cell responds at a rate proportional to the input. Due to the T-channel’s dynamics, we expect the cell’s response to become more nonlinear as the channel becomes more active. To test this hypothesis, we study the response of an in silico relay cell to Poisson spike trains. We first validate our model cell by comparing its responses with in vitro responses. To characterize the model cell’s nonlinearity, we calculate Poisson kernels, an approach akin to white noise analysis but using the randomness of Poisson input spikes instead of Gaussian white noise. We find that a relay cell with active T-channels requires at least a third-order system to achieve a characterization as good as a second-order system for a relay cell without T-channels. Index Terms—Neuroengineering, neuromorphic, relay cell model.
A CMOS circuit implementation of a spiking neuron with bursting and adaptation on a biological timescale
- in Biomedical Circuits and Systems Conference, 2009, BioCAS 2009, IEEE
, 2009
"... adaptation on a biological timescale ..."
(Show Context)
Neuromorphic electronic circuits for building autonomous cognitive systems
- Proceedings of the IEEE (Submitted
"... Member, IEEE Abstract—Several analog and digital brain-inspired electronic systems have been recently proposed as dedicated solutions for fast simulations of spiking neural networks. While these archi-tectures are useful for exploring the computational properties of large-scale models of the nervous ..."
Abstract
-
Cited by 2 (0 self)
- Add to MetaCart
(Show Context)
Member, IEEE Abstract—Several analog and digital brain-inspired electronic systems have been recently proposed as dedicated solutions for fast simulations of spiking neural networks. While these archi-tectures are useful for exploring the computational properties of large-scale models of the nervous system, the challenge of building low-power compact physical artifacts that can behave intelligently in the real-world and exhibit cognitive abilities still remains open. In this paper we propose a set of neu-romorphic engineering solutions to address this challenge. In particular, we review neuromorphic circuits for emulating neural and synaptic dynamics in real-time and discuss the role of biophysically realistic temporal dynamics in hardware neural processing architectures; we review the challenges of realizing spike-based plasticity mechanisms in real physical systems and present examples of analog electronic circuits that implement them; we describe the computational properties of recurrent neural networks and show how neuromorphic Winner-Take-All circuits can implement working-memory and decision-making mechanisms. We validate the neuromorphic approach proposed with experimental results obtained from our own circuits and systems, and argue how the circuits and networks presented in this work represent a useful set of components for efficiently and elegantly implementing neuromorphic cognition. I.
A Superposable Silicon Synapse with Programmable Reversal Potential
"... Abstract — We present a novel log-domain silicon synapse designed for subthreshold analog operation that emulates common synaptic interactions found in biology. Our circuit models the dynamic gating of ion-channel conductances by emulating the processes of neurotransmitter release–reuptake and recep ..."
Abstract
-
Cited by 1 (1 self)
- Add to MetaCart
(Show Context)
Abstract — We present a novel log-domain silicon synapse designed for subthreshold analog operation that emulates common synaptic interactions found in biology. Our circuit models the dynamic gating of ion-channel conductances by emulating the processes of neurotransmitter release–reuptake and receptor binding–unbinding in a superposable fashion: Only a single circuit is required to model the entire population of synapses (of a given type) that a biological neuron receives. Unlike previous designs, which are strictly excitatory or inhibitory, our silicon synapse implements—for the first time in the log-domain—a programmable reversal potential (i.e., driving force). To demonstrate our design’s scalability, we fabricated in 180nm CMOS an array of 64K silicon neurons, each with four independent superposable synapse circuits occupying 11.0×21.5 µm 2 apiece. After verifying that these synapses have
A Delay-Insensitive Address-Event Link
"... Abstract—We present a delay-insensitive (DI) link that provides virtual point-to-point channels between ports at corresponding locations in two-dimensional arrays on separate chips. A communication, or event, on any particular channel is represented by its input port’s address, which the link encode ..."
Abstract
-
Cited by 1 (0 self)
- Add to MetaCart
(Show Context)
Abstract—We present a delay-insensitive (DI) link that provides virtual point-to-point channels between ports at corresponding locations in two-dimensional arrays on separate chips. A communication, or event, on any particular channel is represented by its input port’s address, which the link encodes, conveys, and decodes. Previous work cut pad-count by transmitting row and column addresses sequentially, appending additional column addresses for concurrent communications in the same row, which are read and written in parallel, thereby boosting throughput. However, a non-DI implementation was used offchip (bundled-data), incurring delay and area penalties when interfaced with DI circuitry used on-chip. The link described here avoids these penalties by using a DI implementation both on- and off-chip (1-of-4 codes). We describe the transmitter’s and receiver’s implementation in detail, including refinements made to ensure efficient and robust operation with arrays as large as 320×960, and provide test results from two chips fabricated in a 0.18µm CMOS process.
Robust Doublet STDP in a Floating-Gate Synapse
"... © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to s ..."
Abstract
- Add to MetaCart
© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [Article DOI:
ARTICLE Communicated by Ralph Etienne-Cummings A Systematic Method for Configuring VLSI Networks of Spiking Neurons
"... An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in ha ..."
Abstract
- Add to MetaCart
An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter
I. SILICON NEURONS
"... Abstract—We present an approach to design spiking silicon neurons based on dynamical systems theory. Dynamical systems theory aids in choosing the appropriate level of abstraction, prescribing a neuron model with the desired dynamics while maintaining simplicity. Further, we provide a procedure to t ..."
Abstract
- Add to MetaCart
(Show Context)
Abstract—We present an approach to design spiking silicon neurons based on dynamical systems theory. Dynamical systems theory aids in choosing the appropriate level of abstraction, prescribing a neuron model with the desired dynamics while maintaining simplicity. Further, we provide a procedure to transform the prescribed equations into subthreshold currentmode circuits. We present a circuit design example, a positivefeedback integrate-and-fire neuron, fabricated in 0.25 µm CMOS. We analyze and characterize the circuit, and demonstrate that it can be configured to exhibit desired behaviors, including spikefrequency adaptation and two forms of bursting. Index Terms—Neuromorphic engineering, silicon neuron, dynamical systems, bifurcation analysis, bursting.
