Results 1  10
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14
Constructive Analysis of Cyclic Circuits
, 1996
"... Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from highlevel language behavioral compiling, and can be used to reduce circuit size. We provide a s ..."
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Cited by 76 (3 self)
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Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from highlevel language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with combinational loops exhibits standard synchronous behavior, and if so, produces an equivalent circuit without combinational loops. We present applications to hardware and software synthesis from the Esterel synchronous programming language.
Convertibility verification and converter synthesis: Two faces of the same coin
 In International Conference on Computer Aided Design ICCAD
, 2002
"... An essential problem in componentbased design is how to compose components designed in isolation. Several approaches have been proposed for specifying component interfaces that capture behavioral aspects such as interaction protocols, and for verifying interface compatibility. Likewise, several app ..."
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Cited by 39 (6 self)
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An essential problem in componentbased design is how to compose components designed in isolation. Several approaches have been proposed for specifying component interfaces that capture behavioral aspects such as interaction protocols, and for verifying interface compatibility. Likewise, several approaches have been developed for synthesizing converters between incompatible protocols. In this paper, we introduce the notion of adaptability as the property that two interfaces have when they can be made compatible by communicating through a converter that meets specified requirements. We show that verifying adaptability and synthesizing an appropriate converter are two faces of the same coin: adaptability can be formalized and solved using a gametheoretic framework, and then the converter can be synthesized as a strategy that always wins the game. Finally we show that this framework can be related to the rectification problem in trace theory. 1.
Sequential Synthesis Using S1S
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2000
"... We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive ..."
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Cited by 16 (7 self)
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We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive a logical expression which yields a single finite state automaton characterizing the set of implementations that can replace a component of a larger design. The power of our approach is demonstrated by the fact that it generalizes immediately to arbitrary interconnection topologies, and to designs containing nondeterminism and fairness. We also describe control aspects of sequential synthesis and relate controller realizability to classical work on program synthesis and tree automata.
Interface Synthesis and Protocol Conversion
 Formal Aspects of Computing
, 2008
"... Abstract. Given deterministic interfaces P and Q, we investigate the problem of synthesising an interface R such that P composed with R refines Q. We show that a solution exists iff P and Q ⊥ are compatible, and the most general solution is given by (P � Q ⊥ ) ⊥ , where P ⊥ is the interface P with ..."
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Cited by 12 (1 self)
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Abstract. Given deterministic interfaces P and Q, we investigate the problem of synthesising an interface R such that P composed with R refines Q. We show that a solution exists iff P and Q ⊥ are compatible, and the most general solution is given by (P � Q ⊥ ) ⊥ , where P ⊥ is the interface P with inputs and outputs interchanged. Remarkably, the result holds both for asynchronous and synchronous interfaces. We model interfaces using the interface automata formalism of de Alfaro and Henzinger. For the synchronous case, we give a new definition of synchronous interface automata based on Mealy machines and show that the result holds for a weak form of nondeterminism, called observable nondeterminism. We also characterise solutions to the synthesis problem in terms of winning input strategies in the automaton (P ⊗ Q ⊥ ) ⊥ , and the most general solution in terms of the most permissive winning strategy. We apply the solution to the synthesis of converters for mismatched protocols in both the asynchronous and synchronous domains. For the asynchronous case, this leads to automatic synthesis of converters for incompatible network protocols. In the synchronous case, we obtain automatic converters for mismatched intellectual property blocks in systemonchip designs. The work reported here is based on earlier work on interface synthesis in [Bha05] for the asynchronous case, and [BR06] for the synchronous one.
Synthesizing Interacting Finite State Machines
 In Proceedings of the International Conference on Computer Design
, 1994
"... We present a mathematical framework for analyzing the synthesis of interacting finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address ..."
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Cited by 6 (5 self)
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We present a mathematical framework for analyzing the synthesis of interacting finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address the issue of FSM realizability. This approach is also applied to synthesizing systems with fairness and timed systems. 1 Introduction The advent of modern VLSI CAD tools has radically changed the process of designing digital systems. The first CAD tools automated the final stages of design, such as placement and routing. As the low level steps became better understood, the focus shifted to the higher stages. In particular logic synthesis, the science of optimizing designs (for various measures such as area, speed, or power) specified at the gate level, has shifted to the forefront of CAD research. Another area rapidly gaining importance is design verification, the study of systematic metho...
Formal Methods in VLSI System Design
, 1996
"... We apply mathematical logic to a number of problems arising in very large scale integration (VLSI) design automation. The first stage of this dissertation is concerned with techniques for the efficient verification of digital systems. We introduce heuristics based on Binary Decision Diagrams for eff ..."
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Cited by 4 (1 self)
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We apply mathematical logic to a number of problems arising in very large scale integration (VLSI) design automation. The first stage of this dissertation is concerned with techniques for the efficient verification of digital systems. We introduce heuristics based on Binary Decision Diagrams for efficiently representing designs specified as gatelevel circuits. We also present an approach to verifying hierarchical designs which uses novel notions of state equivalence to simplify components. The second stage addresses the problem of synthesizing digital designs. We use the logic S1S to demonstrate that the flexibility available for optimizing components in hierarchical designs can be characterized by a finite state automaton. This approach is extended to the problem of synthesizing p...
Verification of Designs Containing Black Boxes
 In EUROMICRO
, 2000
"... Often modern designs contain regions where the implementation of certain components is not (fully) known. These regions are called black boxes in the following. They occur e.g. if different designers work on a project in parallel or if IP cores are used. In this paper an approach based on a symboli ..."
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Cited by 4 (3 self)
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Often modern designs contain regions where the implementation of certain components is not (fully) known. These regions are called black boxes in the following. They occur e.g. if different designers work on a project in parallel or if IP cores are used. In this paper an approach based on a symbolic representation of characteristic functions for verifying circuits with black boxes is presented. We show that by this method more faults can be detected than with pure binary simulation and symbolic simulation using BDDs, respectively, only. This results from the formulation of our algorithm that allows implications over the black box. Experimental results are given to show what parts of a design can be proven to be correct, if black boxes are assumed. Of course, the probability for the detection of a fault in general depends on the size of the unknown regions. But fault injection experiments on benchmarks show that for many circuits even up to 90% of the faults are detected, even though ...
Hiding Memory Elements in Induced Hierarchical Verification of SpeedIndependent Circuits
 in Proc. International Workshop on Logic Synthesis
, 1998
"... : The goal of induced hierarchical verification techniques is to automatically create hierarchy in an originally flat circuit in order to decompose the verification problem (i.e., checking hazardfreedom and conformance to a specification) into that of verifying a set of smaller subcircuits. Existi ..."
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Cited by 3 (1 self)
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: The goal of induced hierarchical verification techniques is to automatically create hierarchy in an originally flat circuit in order to decompose the verification problem (i.e., checking hazardfreedom and conformance to a specification) into that of verifying a set of smaller subcircuits. Existing induced hierarchical verification techniques for speedindependent circuits are limited because the output of any memory element (e.g., Muller Celement) must be a subcircuit output (i.e., memory elements cannot be hidden). Consequently, these techniques have exponential complexity in the number of memory element outputs in the circuit. In this paper, we prove that this limitation is not fundamental. Specifically, we develop a theoretical framework for induced hierarchical verification of speedindependent circuits and show that, under certain welldefined conditions, subcircuits can be formed which may contain memory elements whose outputs are internal to the subcircuit. The key step ...
Optimizing Designs Containing Black Boxes
 34th Design Automation Conference
, 1997
"... We define a notion of equivalence for designs containing black boxes i.e., components whose functionality is not known; these arise naturally in the course of hierarchical design. Using this notion, we describe a sound and complete methodology for optimizing such designs. 1 ..."
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Cited by 3 (0 self)
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We define a notion of equivalence for designs containing black boxes i.e., components whose functionality is not known; these arise naturally in the course of hierarchical design. Using this notion, we describe a sound and complete methodology for optimizing such designs. 1