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D.: A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface
- In: Proceedings of the 9 th FORMATS International Conference, LNCS
, 2011
"... Abstract. In this paper we present a Design-for-Verification framework for a Configurable Performance-Critical Communication Interface. To manage the inherent complexity of the problem we decomposed the interface into independent parametrisable communication blocks. Tock-CSP was then used to model t ..."
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Abstract. In this paper we present a Design-for-Verification framework for a Configurable Performance-Critical Communication Interface. To manage the inherent complexity of the problem we decomposed the interface into independent parametrisable communication blocks. Tock-CSP was then used to model the timing and functional specifications of our interface. The FDR model checker and its tau-priority model were used to prove that the properties of the configured interface are within the properties of targeted communication protocols.
Towards a formally verified network-on-chip
- in Formal Methods in Computer-Aided Design, 2009. FMCAD 2009
, 2009
"... Abstract—Multi-Processor Systems-on-Chip (MPSoC) designs are constructed by assembling pre-designed parameterized com-ponents. Communications are crucial to their overall function-ality and performance. Formal verification methods have been intensively applied to processing elements, e.g., microproc ..."
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Abstract—Multi-Processor Systems-on-Chip (MPSoC) designs are constructed by assembling pre-designed parameterized com-ponents. Communications are crucial to their overall function-ality and performance. Formal verification methods have been intensively applied to processing elements, e.g., microprocessors. Very little work has been done with respect to communication modules. We present the formal specification of a packet switched NoC and its proven refinement. At the specification level, routing decisions are computed at once before packets get injected in the network. In the implementation, routing decisions are distributed over each individual node. We prove that the implementation be-haves according to its specification for a 2D-mesh NoC. All models and proofs have been checked using the ACL2 theorem proving system. To the best of our knowledge, this work constitutes the first cross-layer verification of on-chip communication networks. I.
A Symbolic Execution Framework for
"... Abstract—This work aims to address the well-known and acute challenge of functional validation for complex, contemporary microarchitectural circuit designs. We provide a new formal framework for algorithm level modelling—design modelling at a high abstraction level, focused exclusively on function a ..."
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Abstract—This work aims to address the well-known and acute challenge of functional validation for complex, contemporary microarchitectural circuit designs. We provide a new formal framework for algorithm level modelling—design modelling at a high abstraction level, focused exclusively on function and State Machines with synchronous parallel execution, sequential execution, and nondeterminism. To express models we propose an executable, object-oriented Architecture Specification Language with rich data types and a well-defined formal semantics, based initially on Microsoft’s AsmL. We describe an experimental framework for direct symbolic execution of models in this language, intended as a basis for both property and refinement verification, as well as design exploration. We explain and illustrate our approach through a case study, the modelling a simple µop scheduler and its refinement towards a design model for circuit implementation. We aim to show the utility of our language and symbolic execution framework for exploring microarchitectural algorithm and to validate designs using dynamic or formal techniques, yielding more productive convergence to high quality implementations. I.
