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HighSpeed ParallelPrefix Modulo 2n ÿ 1 Adders
"... AbstractÐA novel parallelprefix architecture for high speed modulo 2n ÿ 1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional endaround carry approach. Static CMOS implementations verify that the propos ..."
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AbstractÐA novel parallelprefix architecture for high speed modulo 2n ÿ 1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional endaround carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallelprefix or carry lookahead structures. Index TermsÐModulo 2n ÿ 1 adders, parallelprefix adders, carry lookahead adders, VLSI design. æ 1
MODULO 2n + 1 MAC UNIT
"... Modulo 2n + 1 arithmetic has a variety of applications in several fields like cryptography, pseudorandom number generation, eliminating roundoff errors in convolution computations, etc. Residue Number System (RNS) represents a number in the range of [0, 2n] using n + 1 bits. The RNS is an arithmeti ..."
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Modulo 2n + 1 arithmetic has a variety of applications in several fields like cryptography, pseudorandom number generation, eliminating roundoff errors in convolution computations, etc. Residue Number System (RNS) represents a number in the range of [0, 2n] using n + 1 bits. The RNS is an arithmetic system which decomposes a number into parts (residues) and performs arithmetic operations in parallel for each residue without the need of carry propagation among them, leading to significant speed up over the corresponding binary operations. RNS is well suited to applications that are rich of addition/subtraction and multiplication operations and has been adopted in the design of digital signal processors. The complexity of modulo 2n + 1 arithmetic operation such as addition and multiplication can be reduced by designing an efficient modulo 2n + 1 adder and modulo 2n + 1 multiplier. Both the addition and multiplication are combined together to form a multiply and accumulate (MAC) unit. Diminishedone number representation is employed in this MAC unit. In the diminishedone number system, each number X is represented by X * = X – 1 and the representation of 0 is treated in a special way. Therefore, diminishedone modulo 2n + 1 circuits require only n bits for their number representations. An efficient modulo 2n + 1 MAC unit is presented in this paper. A diminishedone modulo 2n + 1 adder using parallelprefix tree for carry computation and modulo 2n + 1 multiplier based on dadda tree architecture is used for MAC architecture. The proposed MAC unit is analysed using various tools like ModelSim 10.1b for logical verification and for synthesizing Leonardo Spectrum LS 2009 a_6.