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Interfacing binary networks to multi-valued signals
- in Supplementary Proceedings of the Joint International Conference ICANN/ICONIP 2003
, 2003
"... Abstract — Data processing of real-world problems usually leads to the use of quasi-continuous discrete quantities. If artifi-cial neural networks are to be used they need to interface multi-valued signals. For the case of a mixed-mode analog hardware neural network of neurons with binary inputs and ..."
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Abstract — Data processing of real-world problems usually leads to the use of quasi-continuous discrete quantities. If artifi-cial neural networks are to be used they need to interface multi-valued signals. For the case of a mixed-mode analog hardware neural network of neurons with binary inputs and outputs, this paper demonstrates that it is possible to combine these to form integer input and output neurons. A precision of 6 bits has been reached. Together with programmable synapses connecting -bit neurons to -bit neurons they represent parameterizable building blocks useful for networks of variable precision. I.
Image Recognition Using Merged/Mixed Analog-Digital Architecture
"... Abstract: Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power con-sumption is required. This paper proposes a VLSI c ..."
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Abstract: Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power con-sumption is required. This paper proposes a VLSI convolutional network architecture using a hybrid approach composed of pulse-width modulation (PWM) and digital circuits. We call this approach merged/mixed analog-digital architecture. The VLSI chip includes PWM neuron circuits, PWM/digital converters, digital adder-subtracters, and digital memory. We have designed and fabricated a VLSI chip by using a 0.35 m CMOS process. The VLSI chip can perform 6-bit precision convolution calculations for an image of 100100 pixels with a receptive field area of up to 2020 pixels within 5 ms, which means a performance of 2 GOPS. Power consumption of PWM neuron circuits is measured to be 20 mW. We have verified successful operations using a fabricated VLSI chip. 1.
Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms
"... Abstract. This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor resides in the con-figurable logic, it can execute common genetic operators like crossover and mutation with a ..."
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Abstract. This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor resides in the con-figurable logic, it can execute common genetic operators like crossover and mutation with a targeted data throughput of 420 MByte/s. Together with the microprocessor core, a complex evolutionary algorithm can be developed in software, but is processed at the speed of dedicated hard-ware. 1
