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25
ON THE HARDWARESOFTWARE PARTITIONING PROBLEM: system modeling and partitioning techniques
 ACM Transactions on Design Automation of Electronic Systems
, 2003
"... This paper presents an indepth study of several system partitioning procedures. It is based on the appropriate formulation of a general system model, being therefore independent of either the particular codesign problem or the specific partitioning procedure. The techniques under study are a knowl ..."
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Cited by 30 (0 self)
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This paper presents an indepth study of several system partitioning procedures. It is based on the appropriate formulation of a general system model, being therefore independent of either the particular codesign problem or the specific partitioning procedure. The techniques under study are a knowledgebased system and three classical circuit partitioning algorithms (Simulated Annealing, Kernighan&Lin and Hierarchical Clustering). The former has been entirely proposed by the authors in previous works while the later have been properly extended to deal with system level issues. We will show how the way the problem is solved biases the results obtained, regarding both quality and convergence rate. Consequently it is extremely important to choose the most suitable technique for the particular codesign problem that is being confronted.
HIERARCHICAL SYNTHESIS OF EMBEDDED SYSTEMS USING EVOLUTIONARY ALGORITHMS  A MultiObjective Approach
, 2003
"... In this chapter, we propose an approach for the synthesis of heterogenous embedded systems, including allocation and binding problems. For solving these in general NPcomplete problems, Evolutionary Algorithms have been proven to provide good solutions for search spaces of moderate size. For realist ..."
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Cited by 11 (4 self)
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In this chapter, we propose an approach for the synthesis of heterogenous embedded systems, including allocation and binding problems. For solving these in general NPcomplete problems, Evolutionary Algorithms have been proven to provide good solutions for search spaces of moderate size. For realistic embedded system applications, however, two more challenges must be considered: a) the complexity of the search space, and b) the multiobjective nature of the optimization problem to solve. I.e., the desired result of system synthesis is a design space exploration that provides the set of socalled Paretooptimal solutions or an approximation thereof instead of just a single solution. Here, we propose a solution based on a MultiObjective Evolutionary Algorithm (MOEA) which denotes a class of Evolutionary Algorithms that have recently proposed for design space exploration problems. Secondly, in order to reduce the complexity of typical search spaces, we propose a hierarchical problem and solution structure.
Efficient search space exploration for HWSW partitioning
 Hardware/Software Codesign and System Synthesis International Conference
, 2004
"... Hardware/software (HWSW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for traditional partitioning approaches – as we move to more complex and heterogeneous SOCs – is the lack of efficient exploration of the large space ..."
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Cited by 9 (0 self)
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Hardware/software (HWSW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for traditional partitioning approaches – as we move to more complex and heterogeneous SOCs – is the lack of efficient exploration of the large space of possible HW/SW configurations, coupled with the inability to efficiently scale up with larger problem sizes. In this paper, we make two contributions for HWSW partitioning of applications represented as procedural callgraphs: 1) we prove that during partitioning, the execution time metric for moving a vertex needs to be updated only for the immediate neighbours of the vertex, rather than for all ancestors along paths to the root vertex; consequently, we observe faster runtimes for movebased partitioning algorithms such as Simulated Annealing (SA), allowing call graphs with thousands of vertices to be processed in less than a second, and 2) we devise a new cost function for SA that allows frequent discovery of better partitioning solutions by searching spaces overlooked by traditional SA cost functions. We present experimental results on a very large design space, where several thousand configurations are explored in minutes as compared to several hours or days using a traditional SA formulation. Furthermore, our approach is frequently able to locate better design points with over 10 % improvement in application execution time compared to the solutions generated by a KernighanLin partitioning algorithm starting with an allSW partitioning.
Iterative Schedule Optimisation for Voltage Scalable Distributed Embedded Systems
 ACM Trans. on Embedded Computing Systems
, 2003
"... this paper falls into the class of static voltage schedulers ..."
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Cited by 4 (2 self)
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this paper falls into the class of static voltage schedulers
Very fast simulated annealing for HWSW partitioning
, 2004
"... Hardware/software (HWSW) partitioning is a key problem in the codesign of embedded systems and has been studied extensively in the past. With the wide availability of commercial platforms such as the VirtexII Pro series from Xilinx that integrate processors with reconfigurable logic, one major exi ..."
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Cited by 3 (1 self)
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Hardware/software (HWSW) partitioning is a key problem in the codesign of embedded systems and has been studied extensively in the past. With the wide availability of commercial platforms such as the VirtexII Pro series from Xilinx that integrate processors with reconfigurable logic, one major existing challenge is the lack of efficient algorithms that can generate very highquality solutions by exploring a huge HW/SW exploration space the key criterion is to obtain such solutions at a speed suitable for integration into a compilerbased partitioner. In this report, we make two contributions for HWSW partitioning of applications specified as procedural callgraphs: 1) We prove that during partitioning, the execution time metric for moving a vertex needs to be updated only for the immediate neighbours of the vertex, rather than for all ancestors along paths to the root vertex. This enables movebased partitioning algorithms such as Simulated Annealing (SA) to execute significantly faster, allowing call graphs with thousands of vertices to be processed in less than half a second 2) Additionally, we devise a new cost function for SA that enables searching of spaces overlooked by traditional SA cost functions for HWSW partitioning, allowing the discovery of additional partitioning
Fast Rescheduling of MultiRate Systems for HW/SW Partitioning Algorithms
, 2005
"... In modern designs for heterogeneous systems with their extreme requirements on power consumption, execution time, silicon area and timetomarket, the HW/SW partitioning problem belongs to the most challenging ones. Usually its formulation, based on task or process graphs with complex communication ..."
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Cited by 3 (2 self)
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In modern designs for heterogeneous systems with their extreme requirements on power consumption, execution time, silicon area and timetomarket, the HW/SW partitioning problem belongs to the most challenging ones. Usually its formulation, based on task or process graphs with complex communication models, is intractable. Moreover most partitioning problems embed another NPhard problem in its core: a huge number of valid schedules exist for a single partitioning solution. Powerful heuristics for the partitioning problem rely on list scheduling techniques to solve this scheduling problem. This paper is based on a rescheduling algorithm that performs better than popular list scheduling techniques and still preserves linear complexity by reusing former schedules. A sophisticated communication model is introduced and the rescheduling algorithm is modified to serve multicore architectures with linear runtime.
A Dynamically Constrained Genetic Algorithm For Hardwaresoftware Partitioning
 In Proc. of the 8th annual conf. on Genetic and evolutionary computation GECCO’06
, 2006
"... In this article, we describe the application of an enhanced genetic algorithm to the problem of hardwaresoftware codesign. Starting from a source code written in a highlevel language our algorithm determines, using a dynamicallyweighted fitness function, the most interesting code parts of the pro ..."
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In this article, we describe the application of an enhanced genetic algorithm to the problem of hardwaresoftware codesign. Starting from a source code written in a highlevel language our algorithm determines, using a dynamicallyweighted fitness function, the most interesting code parts of the program to be implemented in hardware, given a limited amount of resources, in order to achieve the greatest overall execution speedup. The novelty of our approach resides in the tremendous reduction of the search space obtained by specific optimizations passes that are conducted on each generation. Moreover, by considering different granularities during the evolution process, very fast and effective convergence (in the order of a few seconds) can thus be attained. The partitioning obtained can then be used to build the different functional units of a processor well suited for a large customization, thanks to its architecture that uses only one instruction, Move
Finding optimal hardware/software partitions
 FORMAL METHODS IN SYSTEM DESIGN
, 2007
"... Most previous approaches to hardware/software partitioning considered heuristic solutions. In contrast, this paper presents an exact algorithm for the problem based on branchandbound. Several techniques are investigated to speed up the algorithm, including bounds based on linear programming, a cus ..."
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Cited by 2 (1 self)
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Most previous approaches to hardware/software partitioning considered heuristic solutions. In contrast, this paper presents an exact algorithm for the problem based on branchandbound. Several techniques are investigated to speed up the algorithm, including bounds based on linear programming, a custom inference engine to make the most out of the inferred information, advanced necessary conditions for partial solutions, and different heuristics to obtain highquality initial solutions. It is demonstrated with empirical measurements that the resulting algorithm can solve highly complex partitioning problems in reasonable time. Moreover, it is about ten times faster than a previous exact algorithm based on integer linear programming. The presented methods can also be useful in other related optimization problems.
Improvements of the GCLP Algorithm for HW/SW Partitioning of Task Graphs
 in Proc. of the 4th IASTED Int. Conf. on Circuits, Signals, and Systems (CSS
, 2006
"... HW/SW partitioning of modern heterogeneous systems, which combine signal processing as well as multimedia applications, is usually performed on a task or process graph representation. As this optimisation problem is known to be NPhard, existing partitioning techniques rely on heuristic methods to t ..."
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HW/SW partitioning of modern heterogeneous systems, which combine signal processing as well as multimedia applications, is usually performed on a task or process graph representation. As this optimisation problem is known to be NPhard, existing partitioning techniques rely on heuristic methods to traverse the vast search space. The Global Criticality/Local Phase (GCLP) algorithm, initially introduced by Kalavade and Lee as an integral part of the Ptolemy work suite, has been frequently referred to as fast and powerful technique to generate high quality solutions for a combined partitioning/scheduling problem. In this work the internal mechanisms of the GCLP algorithm have been thoroughly analysed and several modifications are proposed that lead either to a significant increase of the quality of the obtained solutions without affecting the computation time of the algorithm or to a substantially lower computation time while increasing the output of valid partitioning solutions.