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26
Security as a new dimension in embedded system design
- In Proceedings of the 41st Design Automation Conference (DAC ’04
, 2004
"... The growing number of instances of breaches in information security in the last few years has created a compelling case for efforts towards secure electronic systems. Embedded systems, which will be ubiquitously used to capture, store, manipulate, and access data of a sensitive nature, pose several ..."
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Cited by 61 (4 self)
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The growing number of instances of breaches in information security in the last few years has created a compelling case for efforts towards secure electronic systems. Embedded systems, which will be ubiquitously used to capture, store, manipulate, and access data of a sensitive nature, pose several unique and interesting security challenges. Security has been the subject of intensive research in the areas of cryptography, computing, and networking. However, despite these efforts, security is often mis-construed by designers as the hardware or software implementation of specific cryptographic algorithms and security protocols. In reality, it is an entirely new metric that designers should consider throughout the design process, along with other metrics such as cost, performance, and power. This paper is intended to introduce embedded system designers and design tool developers to the challenges involved in designing
Robust Protection Against Fault-Injection Attacks of Smart Cards Implementing the Advanced Encryption Standard
- Proc. Int. Conference on Dependable Systems and Networks (DNS
, 2004
"... We present a method of protecting a hardware implementation of the Advanced Encryption Standard (AES) against a side-channel attack known as Differential Fault Analysis attack. The method uses systematic nonlinear (cubic) robust error detecting codes. Errordetecting capabilities of these codes depen ..."
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Cited by 43 (18 self)
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We present a method of protecting a hardware implementation of the Advanced Encryption Standard (AES) against a side-channel attack known as Differential Fault Analysis attack. The method uses systematic nonlinear (cubic) robust error detecting codes. Errordetecting capabilities of these codes depend not just on error patterns (as in the case of linear codes) but also on data at the output of the device which is protected by the code and this data is unknown to the attacker since it depends on the secret key. In addition to this, the proposed nonlinear (n,k)-codes reduce the fraction of undetectable errors from 2 r − 2 to 2 r − as compared to the corresponding (n,k) linear code (where n-k=r and k>=r). We also present results on a FPGA implementation of the proposed protection scheme for AES as well as simulation results on efficiency of the robust codes. 1.
Tamper Resistance Mechanisms for Secure, Embedded Systems
- Proc. 17th Int‟l Conf. Very Large Scale Integration Design (VLSI Design ‟04
, 2004
"... Security is a concern in the design of a wide range of embedded sys-tems. Extensive research has been devoted to the development of cryptographic algorithms that provide the theoretical underpinnings of information security. Functional security mechanisms, such as se-curity protocols, suitably emplo ..."
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Cited by 40 (1 self)
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Security is a concern in the design of a wide range of embedded sys-tems. Extensive research has been devoted to the development of cryptographic algorithms that provide the theoretical underpinnings of information security. Functional security mechanisms, such as se-curity protocols, suitably employ these mathematical primitives in order to achieve the desired security objectives. However, functional security mechanisms alone cannot ensure security, since most em-bedded systems present attackers with an abundance of opportunities to observe or interfere with their implementation, and hence to com-promise their theoretical strength. This paper surveys various tamper or attack techniques, and ex-plains how they can be used to undermine or weaken security func-tions in embedded systems. Tamper-resistant design refers to the pro-cess of designing a system architecture and implementation that is resistant to such attacks. We outline approaches that have been pro-posed to design tamper-resistant embedded systems, with examples drawn from recent commercial products. 1
Place And Route For Secure Standard Cell Design
- CARDIS, 2004
, 2004
"... Side channel attacks can be effectively addressed at the circuit level by using dynamic differential logic styles. A key problem is to guarantee a balanced capacitive load at the differential outputs of the logic gates. The main contribution to this load is the capacitance associated with the routin ..."
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Cited by 27 (2 self)
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Side channel attacks can be effectively addressed at the circuit level by using dynamic differential logic styles. A key problem is to guarantee a balanced capacitive load at the differential outputs of the logic gates. The main contribution to this load is the capacitance associated with the routing between cells. This paper describes a novel design methodology to route a design in which multiple differential pairs are present. The methodology is able to route 20K+ differential routes. The differential routes are always routed in adjacent tracks and the parasitic effects between the two wires of each differential pair are balanced. The methodology is developed on top of a commercially available EDA tool. It has been developed as part of a secure digital design flow to protect security applications against Differential Power Analysis attacks. Experimental results indicate that a perfect protection is attainable with the aid of the proposed differential routing strategy.
A Digital Design Flow for Secure Integrated Circuits
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2006
"... Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digit ..."
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Cited by 26 (4 self)
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Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal–oxide–semiconductor (CMOS) gates. This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs. The design flow starts from a normal design in a hardware description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) or Verilog and provides a direct path to an SCA-resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. The basis for power analysis attack resistance is discussed. This paper describes how to adjust the library databases such that the regular single-ended static CMOS standard cells implement a dynamic and differential logic style and such that 20 000+ differential nets can be routed in parallel. This paper also explains how to modify the constraints and rules files for the synthesis, place, and differential route procedures. Measurement-based experimental results have demonstrated that the secure digital design flow is a functional technique to thwart side-channel power analysis. It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-µm CMOS.
Verbauwhede “Design Method for Constant Power Consumption of Differential Logic Circuits
- Proceedings Design, Automation and Test in Europe
, 2005
"... Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To address this issue, logic gates that have a constant power diss ..."
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Cited by 10 (0 self)
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Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To address this issue, logic gates that have a constant power dissipation independent of the input signals, are used in security ICs. This paper presents a design methodology to create fully connected differential pull down networks. Fully connected differential pull down networks are transistor networks that for any complementary input combination connect all the internal nodes of the network to one of the external nodes of the network. They are memoryless and for that reason have a constant load capacitance and power consumption. This type of networks is used in specialized logic gates to guarantee a constant contribution of the internal nodes into the total power consumption of the logic gate. 1
Synthesis of Secure FPGA Implementations
- B
, 2004
"... This paper describes the synthesis of Dynamic Differential Logic to increase the resistance of FPGA implementations against Differential Power Analysis. The synthesis procedure is developed and a detailed description is given of how EDA tools should be used appropriately to implement a secure dig ..."
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Cited by 5 (0 self)
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This paper describes the synthesis of Dynamic Differential Logic to increase the resistance of FPGA implementations against Differential Power Analysis. The synthesis procedure is developed and a detailed description is given of how EDA tools should be used appropriately to implement a secure digital design flow. Compared with an existing technique to implement Dynamic Differential Logic on FPGA, the technique saves a factor 2 in slice utilization. Experimental results also indicate that a secure version of the AES encryption algorithm can now be implemented with a mere 50% increase in time delay and 90% increase in slice utilization when compared with a normal non-secure single ended implementation.
Gate Transfer Level Synthesis as an Automated Approach to Fine-Grain Pipelining
- in Workshop on Token Based Computing (ToBaCo
, 2004
"... this paper. The use of dynamic logic is attractive for synchronous designs but no dynamic gate standard cell libraries exist so far mostly due to the late input arrival, charge sharing and noise problems eliminated in GTL designs thanks to monotonic data transitions, completion detection and datade ..."
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Cited by 4 (2 self)
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this paper. The use of dynamic logic is attractive for synchronous designs but no dynamic gate standard cell libraries exist so far mostly due to the late input arrival, charge sharing and noise problems eliminated in GTL designs thanks to monotonic data transitions, completion detection and datadependent control
Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security IC’s against Differential Power Analysis
"... Charge Recycling Sense Amplifier Based Logic is presented. This logic is derived from Sense Amplifier Based Logic, which is a logic style with signal independent power consumption that is capable to protect security devices such as Smart Cards against power attacks. Experimental results show that ut ..."
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Cited by 3 (0 self)
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Charge Recycling Sense Amplifier Based Logic is presented. This logic is derived from Sense Amplifier Based Logic, which is a logic style with signal independent power consumption that is capable to protect security devices such as Smart Cards against power attacks. Experimental results show that utilization of advanced circuit techniques save 20 % in power consumption and 63 % in peak supply current and that the logic style preserves the energy masking behavior. I
Automated Pipelining in ASIC Synthesis Methodology: Gate Transfer Level
- IWLS 2004 THIRTEENTH INTERNATIONAL WORKSHOP ON LOGIC AND SYNTHESIS
, 2004
"... The paper presents Gate Transfer Level (GTL) as a general framework for synthesis of industrial complexity asynchronous quasi-delay-insensitive (QDI) circuits. The GTL flow automatically provides the finest degree of pipelining (gate-level) resulting in extremely high-performance designs. Automatic ..."
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Cited by 2 (0 self)
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The paper presents Gate Transfer Level (GTL) as a general framework for synthesis of industrial complexity asynchronous quasi-delay-insensitive (QDI) circuits. The GTL flow automatically provides the finest degree of pipelining (gate-level) resulting in extremely high-performance designs. Automatic gate level pipelining is not possible for synchronous design due to the stage balance problem and clock related overheads (latches, clock skew and jitter). Experimental results show average 4.3x performance increase on MCNC benchmarks compared to synchronous RTL implementation.
