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21
ABC: An Academic IndustrialStrength Verification Tool
"... Abstract. ABC is a publicdomain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on AndInverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of ..."
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Abstract. ABC is a publicdomain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on AndInverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.
Improvements to Combinational Equivalence Checking
 In Proc. Int’l Conf. on ComputerAided Design
, 2006
"... The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). Stateoftheart methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), inte ..."
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Cited by 51 (20 self)
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The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). Stateoftheart methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run SAT on the output (i.e. proving equivalence of the output to constant 0). This paper improves on this method by (a) using more intelligent simulation, (b) using CNFbased SAT with circuitbased decision heuristics, and (c) interleaving SAT with loweffort logic synthesis. Experimental results on public and industrial benchmarks demonstrate substantial reductions in runtime, compared to the current methods. In several cases, the new solver succeeded in solving previously unsolved problems. 1
Scalable Exploration of Functional Dependency by Interpolation and
 Incremental SAT Solving,” in Proc. Int. Conf. ComputerAided Design
, 2007
"... Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, …, gn}, i.e. f = h(g1, …, gn). It plays an important role in many aspects of electronic design automation (EDA), ranging from logic synthesis to formal verification. Prior approac ..."
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Cited by 21 (6 self)
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Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, …, gn}, i.e. f = h(g1, …, gn). It plays an important role in many aspects of electronic design automation (EDA), ranging from logic synthesis to formal verification. Prior approaches to the exploration of functional dependency are based on binary decision diagrams (BDDs), which may not be easily scalable to large designs. This paper proposes a novel reformulation that extensively exploits the capability of modern satisfiability (SAT) solvers. Thereby, functional dependency is detected effectively through incremental SAT solving, and the dependency function h, if it exists, is obtained through Craig interpolation. The main strengths of the proposed approach include: (1) fast detection of functional dependency with modest memory consumption and thus scalable to large designs, (2) a full capacity to handle a large set of base functions and thus discovering dependency whenever exists, and (3) potential application to largescale logic optimization and verification reduction. Experimental results show the proposed method is far superior to prior work and scales well in dealing with the largest ISCAS89 and ITC99 benchmark circuits with up to 200K gates. 1.
Symmetry detection for large boolean functions using circuit representation, simulation and satisfiability
 in DAC
, 2006
"... Classical twovariable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuitbased method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable d ..."
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Cited by 10 (2 self)
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Classical twovariable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuitbased method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable detection of classical symmetries of completelyspecified Boolean functions. This is in contrast to previous incomplete circuitbased methods and complete BDDbased methods. Experimental results demonstrate that the proposed method works for large Boolean functions, for which BDDs cannot be constructed.
Scalable don'tcarebased logic optimization and resynthesis
 Proc. FPGA '09
"... We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reason ..."
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We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don’t cares computed for a window surrounding a node and can take into account external don’t cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean resubstitution. Experimental results on 6input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0 % and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6LUTs, the LUT count and logic level is reduced by 11.8 % and 16.5%, respectively. Experimental results on 6input LUT networks after higheffort synthesis show substantial reductions in area and delay. The longest runtime is about 30 minutes.
SATbased logic optimization and resynthesis
 In Proc. IWLS
, 2007
"... The paper discusses technologyindependent optimization and postmapping resynthesis for combinational logic networks, with emphasis on scalability and efficient implementation. The goal is to develop a resynthesis engine that (a) is capable of substantial logic restructuring, (b) is customizable to ..."
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Cited by 9 (7 self)
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The paper discusses technologyindependent optimization and postmapping resynthesis for combinational logic networks, with emphasis on scalability and efficient implementation. The goal is to develop a resynthesis engine that (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on large industrial designs. The proposed approach is based on several heterogeneous algorithms, which include structural analysis, random and constrained simulation, and manipulation of Boolean functions using a SAT solver. The structural methods include improved windowing, which focuses on reconvergent logic structures rich in functional flexibilities. An efficient simulation scheme is proposed for fast filtering of infeasible resubstitution candidates. Finally, it is shown how a mainstream SAT solver can be minimally modified to bridge it to an interpolation package, which computes Boolean functions of nodes after resynthesis as a byproduct of completed feasibility proofs. Experimental results in this paper were focused on minimizing the number of nets after FPGA mapping. However, other cost functions can be optimized, but the finetuning and experiments with these remains to be done. 1
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD,”
 in Proceedings of International OnLine Testing Symposium,
, 2008
"... Abstract Sets of Pairs of Functions to be Distinguished (SPFD) is ..."
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Cited by 4 (2 self)
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Abstract Sets of Pairs of Functions to be Distinguished (SPFD) is
30.4 LUTBased FPGA Technology Mapping for Reliability
"... As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very important at 45nm and beyond. One common defect point is in the lookup table (LUT) configuration bits, which are crucial to t ..."
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Cited by 4 (0 self)
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As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very important at 45nm and beyond. One common defect point is in the lookup table (LUT) configuration bits, which are crucial to the correct operation of FPGAs. In this work we will present an error analysis technique that is able to efficiently calculate the number of critical bits needed to implement each LUT. We will perform this analysis using a scalable overlapping windowbased method called DCOW (Don'tcare Computation with Overlapping Windows), which allows for accurate and efficient don’tcare lower bound calculations. This new windowing technique can approximate the complete don’t cares within 2.34%, and can be used for many logic synthesis operations. In particular, we apply DCOW to our FPGA mapping algorithm to reduce the number of possible faults. This will allow the design to have a much higher success of functioning correctly when implemented on a faulty FPGA. By using our algorithm, we are able to reduce the number of possible faults by more than 12 % with no area increase.
IPF: InPlace XFilling to Mitigate Soft Errors in SRAMbased FPGAs
"... (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%60 % for the circuits in our experiments) of the total used LUT configuration bits are don’t care bits, and propose to decide the logic values of don’t care bits such that soft errors are reduced. Our approaches ..."
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Cited by 2 (2 self)
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(FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%60 % for the circuits in our experiments) of the total used LUT configuration bits are don’t care bits, and propose to decide the logic values of don’t care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6LUTs, our approaches obtain 20 % chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3 × more chiplevel MTTF improvements and are 128 × faster when compared to the existing best inplace IPD algorithm. Keywordssoft error, mitigation, SRAMbased FPGA, inplace, don’t care
Sequential Logic Rectifications with Approximate SPFDs
"... In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFDbased sequential logic ..."
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In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFDbased sequential logic transformation methodology to tackle the problem with no sacrifice on performance. It first presents an efficient approach to construct approximate SPFDs (aSPFDs) for sequential circuits. Then, it demonstrates an algorithm using aSPFDs to perform the desirable sequential logic transformations using both combinational and sequential don’t cares. Experimental results show the effectiveness and robustness of the approach. 1.