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Cache Games – Bringing Access-Based Cache Attacks on AES to Practice
- 2011 IEEE SYMPOSIUM ON SECURITY AND PRIVACY
, 2011
"... Side channel attacks on cryptographic systems exploit information gained from physical implementations rather than theoretical weaknesses of a scheme. In recent years, major achievements were made for the class of so called access-driven cache attacks. Such attacks exploit the leakage of the memory ..."
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Side channel attacks on cryptographic systems exploit information gained from physical implementations rather than theoretical weaknesses of a scheme. In recent years, major achievements were made for the class of so called access-driven cache attacks. Such attacks exploit the leakage of the memory locations accessed by a victim process. In this paper we consider the AES block cipher and present an attack which is capable of recovering the full secret key in almost realtime for AES-128, requiring only a very limited number of observed encryptions. Unlike previous attacks, we do not require any information about the plaintext (such as its distribution, etc.). Moreover, for the first time, we also show how the plaintext can be recovered without having access to the ciphertext at all. It is the first working attack on AES implementations using compressed tables. There, no efficient techniques to identify the beginning of AES rounds is known, which is the fundamental assumption underlying previous attacks. We have a fully working implementation of our attack which is able to recover AES keys after observing as little as 100 encryptions. It works against the OpenSSL 0.9.8n implementation of AES on Linux systems. Our spy process does not require any special privileges beyond those of a standard Linux user. A contribution of probably independent interest is a denial of service attack on the task scheduler of current Linux systems (CFS), which allows one to observe (on average) every single memory access of a victim process.
FPGA Implementations of Advanced Encryption Standard: a survey
- International Journal of Advances In Engineering & Technology
, 2012
"... Advanced Encryption Standard (AES) is the most secure symmetric encryption technique that has gained worldwide acceptance. The AES based on the Rijndael Algorithm is an efficient cryptographic technique that includes generation of ciphers for encryption and inverse ciphers for decryption. Higher sec ..."
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Advanced Encryption Standard (AES) is the most secure symmetric encryption technique that has gained worldwide acceptance. The AES based on the Rijndael Algorithm is an efficient cryptographic technique that includes generation of ciphers for encryption and inverse ciphers for decryption. Higher security and speed of encryption/decryption is ensured by operations like SubBytes (S-box)/Inv. SubBytes (Inv.S-box), MixColumns/Inv. Mix Columns and Key Scheduling. Extensive research has been conducted into development of S-box /Inv. S-Box and MixColumns/Inv. MixColumns on dedicated ASIC and FPGA to speed up the AES algorithm and to reduce circuit area. This is an attempt, to survey in detail, the work conducted in the aforesaid fields. The prime focus is on the FPGA implementations of optimized novel hardware architectures and algorithms.
Asian Online Journals (www.ajouronline.com) 190 FPGA Implementation of Advance Encryption Standard Using Xilinx System Generator
"... ABSTRACT — This paper presents a resource efficient reconfigurable hardware implementation of Advance Encryption Standard (AES) algorithm using High Level Language (HLL) approach on Field Programmable Gate Array (FPGA) for rapid development. In this work, we use an approach to directly map the desig ..."
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ABSTRACT — This paper presents a resource efficient reconfigurable hardware implementation of Advance Encryption Standard (AES) algorithm using High Level Language (HLL) approach on Field Programmable Gate Array (FPGA) for rapid development. In this work, we use an approach to directly map the design described in a high level package i.e. System Generator on FPGA platforms. This approach is ideal for Encryption functions where the development of data-path architectures can easily be done to provide bit and cycle accurate models. Our approach fills the gap between performance and flexibility by efficiently applying re-configurability. We use primitive level approach and customize all the operations our design by effectively utilizing conventional blocks of Xilinx System Generator to get optimum performance in terms of speed and area. This approach enables us to minimize critical paths in design and increase the overall frequency of design especially for MixColumn and SubByte transform. Our design shows best performance in terms of speed and area as compared with any other software and hardware/software co-design implementation counterparts, it operates at 288.19 MHZ and offers high throughput of 36.864 Gbps.
Workload Characterization of Cryptography Algorithms for Hardware Acceleration
"... Data encryption/decryption has become an essential component for modern information exchange. However, executing these cryptographic algorithms is often associated with huge overhead and the need to reduce this overhead arises correspondingly. In this paper, we select nine widely adopted cryptograph ..."
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Data encryption/decryption has become an essential component for modern information exchange. However, executing these cryptographic algorithms is often associated with huge overhead and the need to reduce this overhead arises correspondingly. In this paper, we select nine widely adopted cryptography algorithms and study their workload characteristics. Different from many previous works, we consider the overhead not only from the perspective of computation but also focusing on the memory access pattern. We break down the function execution time to identify the software bottleneck suitable for hardware acceleration. Then we categorize the operations needed by these algorithms. In particular, we introduce a concept called “Load-Store Block ” (LSB) and perform LSB identification of various algorithms. Our results illustrate that for cryptographic algorithms, the execution rate of most hotspot functions is more than 60%; memory access instruction ratio is mostly more than 60%; and LSB instructions account for more than 30 % for selected benchmarks. Based on our findings, we suggest future directions in designing either the hardware accelerator associated with microprocessor or specific microprocessor for cryptography applications.
Low Cost Fault Tolerant Architecture for Advanced Encryption Standard
"... Abstract- Cryptography is an important subject in secure data communication and secret data base systems. Availability and safety are two necessary properties of the cryptographic systems. Advanced Encryption Standard (AES) is a symmetric cryptography algorithm which it worldwide is used. In this pa ..."
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Abstract- Cryptography is an important subject in secure data communication and secret data base systems. Availability and safety are two necessary properties of the cryptographic systems. Advanced Encryption Standard (AES) is a symmetric cryptography algorithm which it worldwide is used. In this paper, we present a low cost fault tolerant structure for the AES algorithm. A trade-off between reliability and cost is considered in the presented structure. 1-
A Quadtree-based Progressive Lossless Compression Technique for Volumetric Data Sets
"... An efficient technique for progressive lossless compression of volumetric data is described. It is based on the quadtree data structure and exploits the expected similarities between the neighboring slices. The proposed approach has better compression ratio than the octree method. A small amount of ..."
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An efficient technique for progressive lossless compression of volumetric data is described. It is based on the quadtree data structure and exploits the expected similarities between the neighboring slices. The proposed approach has better compression ratio than the octree method. A small amount of memory is required since only two slices need to be located in the memory at a time, which makes it suitable for hardware implementation. A built-in compression in volumetric scanners could considerably reduce the transfer and storage requirements for volumetric medical data.
