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Crosstalk Immune VLSI Design using a Network of PLAs Embedded in a Regular Layout Fabric
 In Proc. of the Intl. Conf. on ComputerAided Design
, 2000
"... We present a VLSI design methodology to address the crosstalk problem, which is becoming increasingly important in Deep SubMicron (DSM) IC design. In our approach, we implement the logic netlist in the form of a network of medium sized PLAs. We utilize two regular layout "fabrics" in our ..."
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Cited by 24 (8 self)
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We present a VLSI design methodology to address the crosstalk problem, which is becoming increasingly important in Deep SubMicron (DSM) IC design. In our approach, we implement the logic netlist in the form of a network of medium sized PLAs. We utilize two regular layout "fabrics" in our methodology, one for areas where PLA logic is implemented, and another for routing regions between such logic blocks. We show that a single PLA implemented in the first fabric style is not only crosstalk immune, but also about 2 smaller and faster than a traditional standard cell based implementation of the same logic. The second fabric, utilized in the routing region between individual PLAs, is also highly crosstalk immune. Additionally, in this fabric, power and ground signals are essentially "prerouted" all over the die.
Using simulation and satisfiability to compute flexibilities in Boolean networks
 IEEE TCAD
, 2006
"... Abstract—Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) com ..."
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Abstract—Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete “don’t cares” (CDCs); 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate nodes for resubstitution. These flexibilities can be used in network optimization to change the network structure while preserving its functionality. In the first two applications, simulation quickly enumerates most of the solutions while SAT detects the remaining solutions. In the last application, simulation efficiently filters out most of the infeasible solutions while SAT checks the remaining candidates. The experimental results confirm that the combination of simulation and SAT offers a computation engine that outperforms binary decision diagrams, which are traditionally used in such applications. Index Terms—Boolean network, logic synthesis, satisfiability, simulation. I.
1 On Complexity of External and Internal Equivalence Checking
, 2006
"... Abstract—We compare the complexity of “internal ” and “external ” equivalence checking. The former is meant for proving the correctness of a synthesis transformation by which circuit N2 is obtained from circuit N1. The latter is meant for proving that circuits N1 and N2 are functionally equivalent w ..."
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Abstract—We compare the complexity of “internal ” and “external ” equivalence checking. The former is meant for proving the correctness of a synthesis transformation by which circuit N2 is obtained from circuit N1. The latter is meant for proving that circuits N1 and N2 are functionally equivalent without making any explicit assumptions about the origin of N1 and N2. We describe logic synthesis procedures that can produce a circuit N2 whose equivalence with the original circuit N1, most likely, can not be efficiently proved by an external equivalence checker. On the other hand, there are internal equivalence checking procedures that easily prove that N1 and N2 are equivalent. We give experimental data showing that these logic synthesis procedures are not a mathematical curiosity but indeed can be used as a powerful method of logic optimization. Index Terms—internal and external equivalence checking, scalable logic synthesis, toggle equivalence, toggle implication. I.