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Behavior of a Computer Based Interlocking System under Transient Hardware Faults

by L. Romano, Z. Kalbarczyk R. K. Iyer, R. K. Iyer - Proc. Pacific Rim Int'l Symp. Fault Tolerant Systems , 1997
"... The * paper addresses the safety analysis and evaluation of a hard real-time, interlocking, railway control system. The major objective is to demonstrate an efficient methodology capable of capturing crucial system dependability characteristics while allowing meaningful results to be obtained with ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
within a reasonable time. The evaluation is done by simulating the execution of the control software under transient hardware faults. The study demonstrates that simulation is a valuable approach to quick and accurate assessment of critical, railway control systems. It allows to study the trade

Comparing the Effects of Intermittent and Transient Hardware Faults on Programs. Workshop on Dependable and Secure Nano-Systems(WDSN),2011 Figure 1 Overview of outcomes for each benchmark

by Jiesheng Wei, Layali Rashid, Karthik Pattabiraman, Sathish Gopalakrishnan
"... Abstract—The trends of shrinking device geometries, lower voltages and higher frequencies in modern processors are ex-pected to increase the rate of intermittent faults. This requires the design of software that are resilient to intermittent faults. There has been substantial research on software sy ..."
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to answer this question by comparing the effects of intermittent and transient hardware faults on programs through fault-injection experiments performed in a micro-architectural simulator for a simple five-stage pipelined processor. We also investigate whether the differences (if any) vary with the length

A Real-Time PES Supporting Runtime State Restoration after Transient Hardware-Faults

by Martin Skambraks, Fernuniversität In Hagen
"... Controlling safety-critical real-time applications that cannot immediately be transferred to a safe state re-quires highly reliable Programmable Electronic Systems (PESs). This demand for fault-tolerance is usually sat-isfied by applying redundant processing structures in-side each PES and, addition ..."
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-started unit must equalise its internal state with that of its redun-dant counterparts before the redundant processing can be rejoined. As a result, redundancy attrition due to transient faults is prevented, since failed channels can be brought back on line. This article states the prob-lems concerned

Transient Fault Detection via Simultaneous Multithreading

by Steven K. Reinhardt, Shubhendu S. Mukherjee - IN PROCEEDINGS OF THE 27TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE , 2000
"... Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardware faults. Most commercial fault-tolerant computers use fully replicated hardware components to detect microprocessor fa ..."
Abstract - Cited by 267 (7 self) - Add to MetaCart
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardware faults. Most commercial fault-tolerant computers use fully replicated hardware components to detect microprocessor

Efficient Software-Based Fault Isolation

by Robert Wahbe, Steven Lucco, Thomas E. Anderson, Susan L. Graham , 1993
"... One way to provide fault isolation among cooperating software modules is to place each in its own address space. However, for tightly-coupled modules, this solution incurs prohibitive context switch overhead, In this paper, we present a software approach to implementing fault isolation within a sing ..."
Abstract - Cited by 777 (12 self) - Add to MetaCart
to an address outside its fault domain. Both these software operations are portable and programming language independent. Our approach poses a tradeoff relative to hardware fault isolation: substantially faster communication between fault domains, at a cost of slightly increased execution time for distrusted

Live Migration of Virtual Machines

by Christopher Clark, Keir Fraser, Steven H, Jakob Gorm Hansen, Eric Jul, Christian Limpach, Ian Pratt, Andrew Warfield - In Proceedings of the 2nd ACM/USENIX Symposium on Networked Systems Design and Implementation (NSDI , 2005
"... Migrating operating system instances across distinct physical hosts is a useful tool for administrators of data centers and clusters: It allows a clean separation between hardware and software, and facilitates fault management, load balancing, and low-level system maintenance. By carrying out the ma ..."
Abstract - Cited by 636 (15 self) - Add to MetaCart
Migrating operating system instances across distinct physical hosts is a useful tool for administrators of data centers and clusters: It allows a clean separation between hardware and software, and facilitates fault management, load balancing, and low-level system maintenance. By carrying out

The Google File System

by Sanjay Ghemawat, Howard Gobioff, Shun-tak Leung - ACM SIGOPS OPERATING SYSTEMS REVIEW , 2003
"... We have designed and implemented the Google File System, a scalable distributed file system for large distributed data-intensive applications. It provides fault tolerance while running on inexpensive commodity hardware, and it delivers high aggregate performance to a large number of clients. While s ..."
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We have designed and implemented the Google File System, a scalable distributed file system for large distributed data-intensive applications. It provides fault tolerance while running on inexpensive commodity hardware, and it delivers high aggregate performance to a large number of clients. While

On the Importance of Checking Cryptographic Protocols for Faults

by Dan Boneh, Richard A. Demillo, Richard J. Lipton , 1997
"... We present a theoretical model for breaking various cryptographic schemes by taking advantage of random hardware faults. We show how to attack certain implementations of RSA and Rabin signatures. An implementation of RSA based on the Chinese Remainder Theorem can be broken using a single erroneous s ..."
Abstract - Cited by 405 (6 self) - Add to MetaCart
We present a theoretical model for breaking various cryptographic schemes by taking advantage of random hardware faults. We show how to attack certain implementations of RSA and Rabin signatures. An implementation of RSA based on the Chinese Remainder Theorem can be broken using a single erroneous

VL2: Scalable and Flexible Data Center Network”,

by Albert Greenberg , James R Hamilton , Navendu Jain , Srikanth Kandula , Changhoon Kim , Parantap Lahiri , David A Maltz , Parveen Patel , Sudipta Sengupta - ACM SIGCOMM Computer Communication Review, , 2009
"... Abstract To be agile and cost e ective, data centers should allow dynamic resource allocation across large server pools. In particular, the data center network should enable any server to be assigned to any service. To meet these goals, we present VL, a practical network architecture that scales t ..."
Abstract - Cited by 461 (12 self) - Add to MetaCart
paths, and () end-system based address resolution to scale to large server pools, without introducing complexity to the network control plane. VL's design is driven by detailed measurements of tra c and fault data from a large operational cloud service provider. VL's implementation

Soft Errors – A Growing Problem

by Peter Ulbrich , 2013
"... ■ Soft-Errors (Transient hardware faults)! ■ Induced by e.g., radiation, glitches, insufficient signal integrity ..."
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■ Soft-Errors (Transient hardware faults)! ■ Induced by e.g., radiation, glitches, insufficient signal integrity
Results 1 - 10 of 4,883