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The Field Programmable Processor Array (FPPA)

by B. Girau, P. Marchal, P. Nussbaum, A. Tisser, Hector Fabio Restrepo
"... The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array, code named FPPA. The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10×10 arra ..."
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The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array, code named FPPA. The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10

Synthesis of Application Specific Programmable Processors

by Kyosun Kim, Ramesh Karri, Miodrag Potkonjak - Proc. of 34th DAC , 1997
"... Processors poses numerous new tasks on behavioral synthesis tools. We address some of them including application bundling. Application Bundling is a synthesis task where n control-data flow graphs are bundled into at most m groups, so that each application belongs to at least one group and throughpu ..."
Abstract - Cited by 11 (0 self) - Add to MetaCart
Processors poses numerous new tasks on behavioral synthesis tools. We address some of them including application bundling. Application Bundling is a synthesis task where n control-data flow graphs are bundled into at most m groups, so that each application belongs to at least one group

Hardware Cost Analysis for Weakly Programmable Processor Arrays

by Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich , 2006
"... Growing complexity and speed requirements in modern application areas such as wireless communication and multimedia in embedded devices demand for flexible and efficient parallel hardware architectures. The inherent parallelism in these application fields has to be reflected at the hardware level to ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
to achieve high performance. Coarse-grained reconfigurable architectures support a high degree of parallelism at multiple levels. In this paper technology-independent hardware cost analysis for a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable

Tiny Application-Specific Programmable Processor for BCH Decoding

by Anthony Van Herrewege, Ingrid Verbauwhede
"... Abstract — We present a novel design for a tiny application-specific programmable processor for BCH decoding. The design is optimized for use in a PUF key extractor, where low-area overhead is extremely important. Due to it’s flexible nature, it can support a wide range of BCH codes. The complete de ..."
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Abstract — We present a novel design for a tiny application-specific programmable processor for BCH decoding. The design is optimized for use in a PUF key extractor, where low-area overhead is extremely important. Due to it’s flexible nature, it can support a wide range of BCH codes. The complete

Power estimation on functional level for programmable processors

by H. Blume, M. Schneider, T. G. Noll - Advances in Radio Science , 2004
"... Abstract. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long Instruction Word (VLIW)-architectures. Special emphasis will ..."
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Abstract. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long Instruction Word (VLIW)-architectures. Special emphasis

Energy efficiency of FPGAs and programmable processors for matrix multiplication

by Ronald Scrofano - In The First IEEE International Conference on Field Programmable Technology (FPT , 2002
"... Advances in their technologies have positioned FPGAs and embedded processors to compete with digital signal processors (DSPs). In this paper, we evaluate the performance in terms of both latency and energy-efficiency of FP-GAs, embedded processors, and DSPs in multiplying two ¢¤£¥ ¢ matrices. As spe ..."
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Advances in their technologies have positioned FPGAs and embedded processors to compete with digital signal processors (DSPs). In this paper, we evaluate the performance in terms of both latency and energy-efficiency of FP-GAs, embedded processors, and DSPs in multiplying two ¢¤£¥ ¢ matrices

Synchronous data flow

by Edward A. Lee, et al. , 1987
"... Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case ..."
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of data flow (either atomic or large grain) in which the number of data samples produced or consumed by each node on each invocation is specified a priori. Nodes can be scheduled statically (at compile time) onto single or parallel programmable processors so the run-time overhead usually associated

An Evolution Programming Approach on Multiple Behaviors for the Design of Application Specific Programmable Processors

by Wei Zhao, Christos A. Papachristou , 1996
"... This paper proposes an Evolution Programming Approach for behavior-level area-efficient design of ASPPs (Application Specific Programmable Processors). This approach, based on a given behavioral-level kernel, randomly transforms each of the input behaviors, then the behavioral kernel is used in the ..."
Abstract - Cited by 13 (0 self) - Add to MetaCart
This paper proposes an Evolution Programming Approach for behavior-level area-efficient design of ASPPs (Application Specific Programmable Processors). This approach, based on a given behavioral-level kernel, randomly transforms each of the input behaviors, then the behavioral kernel is used

A Flexible Code Generation Framework for the Design of Application Specific Programmable Processors

by Francois Charot, et al. , 1999
"... This paper introduces a flexible code generation framework dedicated to the design of application specic programmable processors. This tool allows the user to build specific compilation flows, using a library of modules, implementing flexible compilation passes such as code generation, resource allo ..."
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This paper introduces a flexible code generation framework dedicated to the design of application specic programmable processors. This tool allows the user to build specific compilation flows, using a library of modules, implementing flexible compilation passes such as code generation, resource

Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor

by Chunho Lee , Johnson Kinz, Miodrag Potkonjaky, William H. Mangione-Smith , 1998
"... In this paper we report a framework that makes it possible for a designer to rapidly explore the application-specific programmable processor design space under area constraints. The framework uses a production-quality compiler and simulation tools to synthesize a high performance machine for an appl ..."
Abstract - Cited by 6 (2 self) - Add to MetaCart
In this paper we report a framework that makes it possible for a designer to rapidly explore the application-specific programmable processor design space under area constraints. The framework uses a production-quality compiler and simulation tools to synthesize a high performance machine
Results 1 - 10 of 3,867