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1,096
An Instruction Stream Compression Technique
- Proc of Micro -30
, 1996
"... The performance of instruction memory is a critical factor for both large, high performance applications and for embedded systems. With high performance systems, the bandwidth to the instruction cache can be the limiting factor for execution speed. Code density is often the critical factor for embed ..."
Abstract
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Cited by 6 (0 self)
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for embedded systems. In this report we demonstrate a straightforward technique for compressing the instruction stream for programs. After code generation, the instruction stream is analysed for often reused sequences of instructions from within the program's basic blocks. These patterns of multiple
Fetching instruction streams
- In Procs. of the 36th Intl. Symposium on Microarchitecture
, 2002
"... Fetch performance is a very important factor because it effectively limits the overall processor performance. How-ever, there is little performance advantage in increasing front-end performance beyond what the back-end can con-sume. For each processor design, the target is to build the best possible ..."
Abstract
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Cited by 22 (9 self)
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. Even in the absence of code layout optimizations, fetching instruc-tion streams is still lO % faster than the EV8, and only 4% slower than the trace cache. Fetching instruction streams effectively exploits the spe-cial characteristics of layout optimized codes to provide a high fetch performance, close
Multiple instruction stream processor
- In Proceedings of the 33rd annual international symposium on Computer Architecture
, 2006
"... Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallelism in the software. To support this trend, we present a novel processor architecture called the Multiple Instruction Str ..."
Abstract
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Cited by 12 (2 self)
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Stream Processing (MISP) architecture. MISP introduces the sequencer as a new category of architectural resource, and defines a canonical set of instructions to support user-level inter-sequencer signaling and asynchronous control transfer. MISP allows an application program to directly manage user
Transmission Protocols for Instruction Streams
, 2009
"... Threads as considered in thread algebra model behaviours to be controlled by some execution environment: upon each action performed by a thread, a reply from its execution environment – which takes the action as an instruction to be processed – determines how the thread proceeds. In this paper, we ..."
Abstract
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Cited by 4 (4 self)
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Threads as considered in thread algebra model behaviours to be controlled by some execution environment: upon each action performed by a thread, a reply from its execution environment – which takes the action as an instruction to be processed – determines how the thread proceeds. In this paper, we
Compiler-Directed Instruction Stream Compression
"... Embedded systems are becoming increasingly important, appearing in every aspect of daily life. The cost of these systems is strongly influenced by the cost of the processor chip. The chip cost, in turn, is dominated by the die size. By compressing embedded software the space devoted to instruction m ..."
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memory can be reduced, lowering costs. Alternatively, more fully-featured software can be provided without increasing costs. We present a compiler-controlled instruction stream compression method. Our implementation uses similar code templates to create, in essence, lightweight functions. These functions
MISC: A Multiple Instruction Stream Computer
- In Proc of the 25th. Ann. Symp. on Microarchitecture
, 1992
"... This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parall ..."
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Cited by 24 (4 self)
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This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed
A Protocol for Instruction Stream Processing
, 2009
"... The behaviour produced by an instruction sequence under execution is a behaviour to be controlled by some execution environment: each step performed actuates the processing of an instruction by the execution environment and a reply returned at completion of the processing determines how the behaviou ..."
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the behaviour proceeds. In this paper, we are concerned with the case where the processing takes place remotely. We describe a protocol to deal with the case where the behaviour produced by an instruction sequence under execution leads to the generation of a stream of instructions to be processed and a remote
Code Scheduling for Multiple Instruction Stream Architectures
, 1993
"... Extensive research as been done on extracting parallelism from single instruction stream processors. This paper presents our investigation i to ways to modify MIMD architectures to allow them to extract he instruction level parallelism achieved by current superscalar and VLIW machines. A new archite ..."
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Extensive research as been done on extracting parallelism from single instruction stream processors. This paper presents our investigation i to ways to modify MIMD architectures to allow them to extract he instruction level parallelism achieved by current superscalar and VLIW machines. A new
Code Scheduling for Multiple Instruction Stream Architectures
- International Journal of Parallel Processing
, 1994
"... Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents our investigation into ways to modify MIMD architectures to allow them to extract the instruction level parallelism achieved by current superscalar and VLIW machines. A new archi ..."
Abstract
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Cited by 4 (0 self)
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Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents our investigation into ways to modify MIMD architectures to allow them to extract the instruction level parallelism achieved by current superscalar and VLIW machines. A new
Results 1 - 10
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