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Results 1 - 10
of
104
and Dissertations
"... (Name of Style Manual used in this Study) The status of hydration of forty elderly, who were residing in Lyngblomsten Care Center in St. Paul, Minnesota, was investigated in this study. The subjects were further separated into two groups using the Minimum Data Set (MDS) screening. The MDS was used t ..."
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subject was recorded for three consecutive days by the ii researcher and staff members. Using the the data collected, the total calorie and water intakes were calculated using the Food Processor Plus software. The actual fluid intake
Nutrition Examination Survey and the ESHA Food Processor
, 2001
"... The objective of this study was to assess agreement on nutrient intake between the nutrient database of the First National Health and Nutrition Examination Survey (NHANES I) and an up-to-date (December 1998) nutrient database, the ESHA Food Processor. Analysis was conducted among 11,303 NHANES I par ..."
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participants aged 25– 74 years in 1971–1975 who had undergone dietary assessment. A list of all unique foods consumed was obtained from a single 24-hour dietary recall questionnaire administered during the baseline NHANES I visit. Foods on the list were matched to foods in the ESHA Food Processor software
A Low-Cost At-Speed Bist Architecture for Embedded Processor and Sram
- Cores,” J. Electronic Testing: Theory and Applications
, 2004
"... Abstract. We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test m ..."
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Cited by 3 (0 self)
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Abstract. We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test
A performance counter architecture for computing accurate CPI components
- In ASPLOS
, 2006
"... A common way of representing processor performance is to use Cycles per Instruction (CPI) ‘stacks ’ which break performance into a baseline CPI plus a number of individual miss event CPI components. CPI stacks can be very helpful in gaining insight into the behavior of an application on a given micr ..."
Abstract
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Cited by 55 (8 self)
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A common way of representing processor performance is to use Cycles per Instruction (CPI) ‘stacks ’ which break performance into a baseline CPI plus a number of individual miss event CPI components. CPI stacks can be very helpful in gaining insight into the behavior of an application on a given
The business case for automated software engineering
- ASE
, 2007
"... Adoption of advanced automated SE (ASE) tools would be more favored if a business case could be made that these tools are more valuable than alternate methods. In theory, software prediction models can be used to make that case. In practice, this is complicated by the ”local tuning ” problem. Normal ..."
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Cited by 4 (2 self)
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. Normally, predictors for software effort and defects and threat use local data to tune their predictions. Such local tuning data is often unavailable. This paper shows that assessing the relative merits of different SE methods need not require precise local tunings. STAR1 is a simulated annealer plus a
A STREAMS-based Communications Subsystem in Turing Plus for Protocol Development
, 1991
"... This paper shows how adoption of the UNIX* STREAMS framework permits convenient design of the protocols that the communications subsystem must provide within the HM-Nucleus. The subsystem uses the available resources (shared memory, interprocessor signalling, fast network) to provide an efficient an ..."
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and orderly data-transfer facility among the component processors. It is efficient enough to accommodate the requirements of time-dependent applications (such as real-time processing of speech or image data), yet flexible enough to allow implementation of the high-level protocols needed to support various
Performance Modelling of Concurrent and Parallel Software
"... Software made up of communicating tasks on multiple processors exhibits behaviour which is substantially different from software on a uniprocessor. In particular it exhibits the phenomenon of software bottlenecks. Performance models must incorporate the new effects, which go beyond more conventional ..."
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Software made up of communicating tasks on multiple processors exhibits behaviour which is substantially different from software on a uniprocessor. In particular it exhibits the phenomenon of software bottlenecks. Performance models must incorporate the new effects, which go beyond more
Architectural support for software-defined metadata processing
, 2015
"... Optimized hardware for propagating and checking software-programmable metadata tags can achieve low runtime over-head. We generalize prior work on hardware tagging by considering a generic architecture that supports software-defined policies over metadata of arbitrary size and complex-ity; we introd ..."
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Cited by 8 (1 self)
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and security policies—spatial and temporal memory safety, taint tracking, control-flow integrity, and code and data separation—plus a composite policy that enforces all of them simultaneously. Experiments on SPEC CPU2006 benchmarks with a PUMP-enhanced RISC processor show modest impact on runtime (typically
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy
- System Software Energy. IEEE Symposium on FPGAs for Custom Computing Machines (FCCM
, 2002
"... We examine the energy savings possible by re-mapping critical software loops from a microprocessor to configurable logic appearing on the same-chip in commodity chips now commercially available. That logic is typically intended to implement peripherals and coprocessors without increasing chip count ..."
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Cited by 12 (8 self)
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periods, thus reducing energy. We use simulations and estimations for a hypothetical device having a 32-bit MIPS processor plus configurable logic, yielding energy savings of 25%, increasing to 39% assuming voltage scaling. We physically measured several examples running on two commercial single
PC/104 Test-Bed for Software GPS Receiver (SGR) and Software Defined Radio (SDR) Applications
"... NAVSYS has developed a PC/104-based Software GPS Receiver (SGR) test-bed that integrates multiple sensors for advanced navigation applications. The sensors compatible with this system can provide GPS, wireless, inertial, and image information. This test-bed provides a low-cost hardware and software ..."
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platform that can rapidly adapt to new waveforms and Software Defined Radio (SDR) applications. PC/104-Plus systems are similar to standard desktop PCs but with a smaller embedded form factor of approximately 4 ” by 4 ” and with lower power consumption. PC/104-Plus boards typically use special stackable
Results 1 - 10
of
104
