dynamics models which can be difficult to parallelize efficiently -- those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed--memory parallel machine which allows for message--passing of data between independently executing processors

and the fast processors. Unless carefully controlled, such architectural optimizations can cause memory accesses to be executed in an order different from what the programmer expects. The set of allowable memory access orderings forms the memory consistency model or event ordering model for an architecture.

Tracing tools are used widely to help analyze, design, and tune both hardware and software systems. This paper describes a tool called Shade which combines efficient instruction-set simulation with a flexible, extensible trace generation capability. Efficiency is achieved by dynamically compiling and caching code to simulate and trace the application program. The user may control the extent of tracing in a variety of ways; arbitrarily detailed application state information may be collected during the simulation, but tracing less translates directly into greater efficiency. Current Shade implementations run on SPARC systems and simulate the SPARC (Versions 8 and 9) and MIPS I instruction sets. This paper describes the capabilities, design, implementation, and performance of Shade, and discusses instruction set emulation in general.

How do executive teams make rapid decisions in the high-velocity microcomputer industry? This inductive study of eight microcomputer firms led lo propositions exploring that question. Fast decision makers use more, not less, information than do slow decision makers. The former also develop more

tracks memory usage and identifies individual memory leals using a novel adaptation of garbage collection techniques. Purify produce standard executable files compatible with existing debuggers, and currently runs on Sun Microsystems ' SPARC family of workstations. Purify's neafly

. This paper describes a high level library (The Nearest Neighbor Tool: NNT) that has been used to parallelize operational weather prediction models. NNT is part of the Scalable Modeling System (SMS), developed at the Forecast Systems Laboratory (FSL). Programs written in NNT rely on SMS's run-time system and port between a wide range of computing platforms, performing well in multiprocessor systems. We show, using examples from operational weather models, how large Fortran 77 codes can be parallelized using NNT. We compare the ease of programmability of NNT and High Performance Fortran (HPF). We also discuss optimizations like data movement overlap (in interprocessor communication and I/O operations), and the minimization of data exchanges through the use of redundant computations. We show that although HPF provides a simpler programming interface, NNT allows for program optimizations that increase performance considerably and still keeps a simple user interface. These optimizations h...

In this paper we take the class of Jacobi-type algorithms and present a systematic way to derive an architecture for execution of the time adaptive QR and QR \Gamma1 algorithms, two members of the class. We know that Jacobi-type algorithms find natural expression in Cordic arithmetic

requiring many breadth-first searches that can be executed simultaneously. Although algo-rithms have implicitly leveraged this abstraction in the past, we provide an explicit, reusable implementation that efficiently maps this abstraction to the GPU, performing more than twice as fast as previous approaches

In this paper, we study the problem of efficiently executing a parallel program composed of N tasks on an N-node hypercube assuming that ffl communications between tasks are irregular i.e. any pair of tasks may want to communicate at any step of the program; ffl communications between any two

Data sets in large applications are often too massive to fit completely inside the computer's internal memory. The resulting input/output communication (or I/O) between fast internal memory and slower external memory (such as disks) can be a major performance bottleneck. In this paper, we