. The BOPS ManArray architecture is presented as a coprocessor platform for the embedded processor domain, consisting of scalable design points. As an array processor, a single architecture definition and tool set supports multiple configurations of processing elements (PEs) from low end single PE

Introduction P. Marwedel 1 New, flexible target technologies As the tendency towards more complex electronic systems continues, many of these systems are equipped with embedded processors. For example, such processors can be found in cars, and in audio-, video-, and telecommunication

multiple heuristics to identify good partitions. Our partitioner can be used to provide the much needed relief to a programmer and could be an important tool in the design space exploration of embedded processor architectures to study the possibility of replacing expensive cache memory by relatively

This paper describes the FlexCC2 register allocation frame- work. FlexCC2 is an optimizing retargetable C compiler for embedded processors, and in particular for DSP processors. Embedded processors often contain features such as irregular and constrained register sets that complicate register

cost due to the lower volumes of customized processors, added hardware development costs, and some factors related to the product development cycle for embedded products. Each is discussed, along with potential, sometimes surprising, solutions.

processor. Used for decades to program desktop operating systems and applications, compilers are among the most widespread software tools. For processor-based embedded systems, however, the use of compilers is less common. Instead, designers still use assembly language to program many embedded applications.

processor. Used for decades to program desktop operating systems and applications, compilers are among the most widespread software tools. For processor-based embedded systems, however, the use of compilers is less common. Instead, designers still use assembly language to program many embedded applications.

Power density has been increasing at an alarming rate in recent processor generations resulting in high on-chip temperature. Higher temperature results in poor reliability and increased leakage current. In this paper, we propose a temperature aware scheduling technique in the context of embedded

Abstract Complexity of embedded applications is growing rapidly. This growth is accompanied by severe implementation contraints on cost, size, performance as well as power. This has resulted in search for expanding the architectural design space for implementing such complex applications. The last

is illustrated on a simple processor used in an embedded web server. The design is verified successfully.