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Table 1: Comparison of two modern embedded processor
1997
Cited by 161
Table 1. Typical Embedded Processor Interrupt Performance
"... In PAGE 3: ...ine. Response and exit times together represent overhead. Worst case performance must be considered during system design since taking the best or average case will lead to condi- tions such as buffer overflow/underflow. While performance for a particular system configuration and operating system may vary, Table1 shows that response time for an interrupt with a full context save for high performance processors is on the order of several microseconds. A major component of response and exit times is saving and restoring the state of the interrupted context.... ..."
Table 3.4: Some embedded processors.
in A Comparison of Address Translation Mechanisms for Virtually-Addressed Caches in Embedded Systems
2002
Table 4. Embedded Processor Test Time Comparison
"... In PAGE 6: ... Total test time during BIST of FPGAs is dominated by two factors: downloading the BIST configurations and retrieving the BIST results at the end of the BIST sequence. We use the time required for full configuration of the FPGA and full configuration memory readback as a baseline for determining the speed-up in test time summarized in Table4 . The download time can be significantly reduced by partial reconfiguration where only those frames that have configuration data changes from one BIST configuration to the next need to be written.... In PAGE 6: ... Using the multiple frame write capability in Virtex-4, there is a further reduction in the number of frames that must be written. It should be noted that the number of frames for multi-frame write in Table4 is given in terms of equivalent frames to account for the additional configuration register commands required to perform the multi-frame write operation. Using dy- namic partial reconfiguration, the contents of the ORA remain unchanged from one BIST configuration to the next such that failure indications can be accumulated in the ORA flip-flops over a sequence of BIST configurations with the results read at the end of the BIST session.... ..."
Table 1 Execution time of the modules running on embedded processor.
2001
"... In PAGE 5: ...v List of tables. Table1 Execution time of the modules running on embedded processor.... ..."
Cited by 1
Table 3: Features and sizes of the workstation processor model and the embedded processor model. Parameter Workstation Model Embedded Model
"... In PAGE 9: ...---25 Table 2: Description of the modifications made to the basic Wattch simulator.--------------------25 Table3 : Features and sizes of the workstation processor model and the embedded processor model. --------------------------------------------------------------------------------------------------26 Table 4: Energy contributions for both the embedded and workstation processors.... In PAGE 34: ...3 Processor Models Two models were used in this study to distinguish between the high-performance market and the portable computing market. Table3 highlights the features of each processor model. The workstation model does not accurately represent any particular processor, but is typical of a modern, high-performance processor.... ..."
Table 4: Energy contributions for both the embedded and workstation processors.
"... In PAGE 9: ...--------------------25 Table 3: Features and sizes of the workstation processor model and the embedded processor model. --------------------------------------------------------------------------------------------------26 Table4 : Energy contributions for both the embedded and workstation processors. ---------------26 Table 5: Subset of SPEC 2000 integer benchmarks used for simulation.... In PAGE 35: ...225 GHz 1.225 GHz The components of the energy model and their contribution to processor energy consumption are listed in Table4 for both the embedded model and the workstation model. In both processors, the clock network consumes the most energy of any single component.... ..."
Table 3. The characteristics of the embedded architectures and processors we compare in this paper.
2002
"... In PAGE 5: ... We compared the density of the VIRAM executables to that for a set of CISC, RISC, and VLIW architectures for high performance embedded processors. Table3 presents the five alternative architectures, as well as the character- istics of the specific processors we studied. We retrieved their code size and all performance scores for the bench- marks from official EEMBC reports submitted by the cor- responding vendors [7].... ..."
Cited by 20
Table 1. Register configurations for a number of embedded and workstation processors.
"... In PAGE 2: ... This lack of agreement in the architecture and compiler research communities is mirrored in commercial processor designs. Table1 shows the register configuration of several embedded and workstation-class processors. While it is true that the register set size on some of these machines was constrained by backward compatibility and cost concerns, it is interesting to note the wide variety of register configurations.... ..."
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