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The Case for a Single-Chip Multiprocessor

by Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, Kunyung Chang - IEEE Computer , 1996
"... Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we look for new ways to use their capabilities effectively. This paper shows that in advanced technologies it is possible to ..."
Abstract - Cited by 440 (6 self) - Add to MetaCart
to implement a single-chip multiproces-sor in the same area as a wide issue superscalar processor. We find that for applications with little parallelism the performance of the two microarchitectures is comparable. For applications with large amounts of parallelism at both the fine and coarse grained levels

Chip Multiprocessors

by William Mary, Kai Tian, Yunlian Jiang, Xipeng Shen, Weizhen Mao, Kai Tian, Yunlian Jiang, Xipeng Shen, Weizhen Mao
"... Abstract—On-chip resource sharing among sibling cores causes resource contention on Chip Multiprocessors (CMP), considerably degrading program performance and system fairness. Job co-scheduling attempts to alleviate the problem by assigning jobs to cores appropriately. Despite many heuristics-based ..."
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Abstract—On-chip resource sharing among sibling cores causes resource contention on Chip Multiprocessors (CMP), considerably degrading program performance and system fairness. Job co-scheduling attempts to alleviate the problem by assigning jobs to cores appropriately. Despite many heuristics

Cooperative caching for chip multiprocessors

by Jichuan Chang - In Proceedings of the 33nd Annual International Symposium on Computer Architecture , 2006
"... Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address these ch ..."
Abstract - Cited by 145 (1 self) - Add to MetaCart
Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address

Interprocessor Communication in Chip Multiprocessors

by Magnus Jahre, Ultrasparc T [mic Abstract
"... Spring 2006The photo on the title page shows the die of Sun Microsystem’s 8-core chip multiprocessor ..."
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Spring 2006The photo on the title page shows the die of Sun Microsystem’s 8-core chip multiprocessor

Adaptive Aggregation on Chip Multiprocessors

by John Cieslewicz, Kenneth A. Ross , 2007
"... The recent introduction of commodity chip multiprocessors requires that the design of core database operations be carefully examined to take full advantage of on-chip parallelism. In this paper we examine aggregation in a multi-core environment, the Sun UltraSPARC T1, a chip multiprocessor with eigh ..."
Abstract - Cited by 33 (4 self) - Add to MetaCart
The recent introduction of commodity chip multiprocessors requires that the design of core database operations be carefully examined to take full advantage of on-chip parallelism. In this paper we examine aggregation in a multi-core environment, the Sun UltraSPARC T1, a chip multiprocessor

Migration in Single Chip Multiprocessors

by Kelly A. Shaw, William J. Dally - Computer Architecture Letters , 2002
"... Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads bas ..."
Abstract - Cited by 11 (0 self) - Add to MetaCart
Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads

Fast Synchronization for Chip Multiprocessors

by Jack Sampson, Rubén González - In ACM SIGARCH Computer Architecture News , 2005
"... This paper presents a novel mechanism for barrier synchronization on chip multi-processors (CMPs). By forcing the invalidation of selected I-cache lines, this mechanism starves threads and thus forces their execution to stop. Threads are let free when all have entered the barrier. We evaluated this ..."
Abstract - Cited by 7 (0 self) - Add to MetaCart
This paper presents a novel mechanism for barrier synchronization on chip multi-processors (CMPs). By forcing the invalidation of selected I-cache lines, this mechanism starves threads and thus forces their execution to stop. Threads are let free when all have entered the barrier. We evaluated

Transient-fault recovery for chip multiprocessors

by Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz - In Proceedings of the 30th Annual International Symposium on Computer Architecture , 2003
"... To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR). CRTR extends the previously-proposed CRT for transient-fault detection in CMPs, and the previously-proposed SRTR for t ..."
Abstract - Cited by 145 (3 self) - Add to MetaCart
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR). CRTR extends the previously-proposed CRT for transient-fault detection in CMPs, and the previously-proposed SRTR

Data Partitioning on Chip Multiprocessors

by John Cieslewicz, Kenneth A. Ross
"... Partitioning is a key database task. In this paper we explore partitioning performance on a chip multiprocessor (CMP) that provides a relatively high degree of on-chip thread-level parallelism. It is therefore important to implement the partitioning algorithm to take advantage of the CMP’s parallel ..."
Abstract - Cited by 15 (3 self) - Add to MetaCart
Partitioning is a key database task. In this paper we explore partitioning performance on a chip multiprocessor (CMP) that provides a relatively high degree of on-chip thread-level parallelism. It is therefore important to implement the partitioning algorithm to take advantage of the CMP’s parallel

Migration in Single Chip Multiprocessors

by unknown authors
"... Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads bas ..."
Abstract - Add to MetaCart
Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads
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