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404
SoC-C: Efficient Programming Abstractions for Heterogeneous Multicore Systems on Chip
"... The architectures of system-on-chip (SoC) platforms found in high-end consumer devices are getting more and more complex as designers strive to deliver increasingly compute-intensive ap-plications on near-constant energy budgets. Workloads running on these platforms require the exploitation of heter ..."
Abstract
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Cited by 4 (1 self)
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The architectures of system-on-chip (SoC) platforms found in high-end consumer devices are getting more and more complex as designers strive to deliver increasingly compute-intensive ap-plications on near-constant energy budgets. Workloads running on these platforms require the exploitation
Merge: A Programming Model for Heterogeneous Multi-core Systems Abstract
"... In this paper we propose the Merge framework, a general purpose programming model for heterogeneous multi-core systems. The Merge framework replaces current ad hoc approaches to parallel programming on heterogeneous platforms with a rigorous, library-based methodology that can automatically distribu ..."
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Cited by 81 (1 self)
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In this paper we propose the Merge framework, a general purpose programming model for heterogeneous multi-core systems. The Merge framework replaces current ad hoc approaches to parallel programming on heterogeneous platforms with a rigorous, library-based methodology that can automatically
McRT-STM: a High Performance Software Transactional Memory System for a Multi-Core Runtime
- In Proc. of the 11th ACM Symp. on Principles and Practice of Parallel Programming
, 2006
"... Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadl ..."
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Cited by 241 (14 self)
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to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming. We describe a software transactional memory (STM) system
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system
- In Proceedings of the 2007 ACM SIGPLAN Conference on Programming Language Design and Implementation
, 2007
"... Future mainstream microprocessors will likely integrate specialized accelerators, such as GPUs, onto a single die to achieve better performance and power efficiency. However, it remains a keen challenge to program such a heterogeneous multi-core platform, since these specialized accelerators feature ..."
Abstract
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Cited by 41 (2 self)
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Future mainstream microprocessors will likely integrate specialized accelerators, such as GPUs, onto a single die to achieve better performance and power efficiency. However, it remains a keen challenge to program such a heterogeneous multi-core platform, since these specialized accelerators
Efficient and scalable scheduling for performance heterogeneous multicore systems
, 2012
"... a b s t r a c t Performance heterogeneous multicore processors (HMP for brevity) consisting of multiple cores with the same instruction set but different performance characteristics (e.g., clock speed, issue width), are of great concern since they are able to deliver higher performance per watt and ..."
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and area for programs with diverse architectural requirements than comparable homogeneous ones. However, such power and area efficiencies of performance heterogeneous multicore systems can only be achieved when workloads are matched with cores according to both the properties of the workload
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC
"... Abstract — The strong demand for complex and high performance embedded system-on-chip (SoC) requires quick turn around design methodology and high performance cores. Thus, there is a clear need for new methodologies supporting efficient and fast design of these systems on complex platforms implement ..."
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Abstract — The strong demand for complex and high performance embedded system-on-chip (SoC) requires quick turn around design methodology and high performance cores. Thus, there is a clear need for new methodologies supporting efficient and fast design of these systems on complex platforms
Programming Experience on Cyclops-64 Multi-Core Chip Architecture 1. Abstract
"... In this paper, we present the design and implementation of a novel toolchain and runtime system which support segmented memory spaces for the IBM Cyclops-64 (C64) computer system- a multiprocessor-on-a-chip architecture. With the powerful support of the toolchain and runtime system, application deve ..."
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In this paper, we present the design and implementation of a novel toolchain and runtime system which support segmented memory spaces for the IBM Cyclops-64 (C64) computer system- a multiprocessor-on-a-chip architecture. With the powerful support of the toolchain and runtime system, application
Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems
"... Abstract—NoCs are an integral part of modern multicore processors, they must continuously support high-throughput low-latency on-chip data communication under a stringent energy budget when system size scales up. Heterogeneous multicore systems further push the limit of NoC design by integrating cor ..."
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Abstract—NoCs are an integral part of modern multicore processors, they must continuously support high-throughput low-latency on-chip data communication under a stringent energy budget when system size scales up. Heterogeneous multicore systems further push the limit of NoC design by integrating
Offload - Automating Code Migration to Heterogeneous Multicore Systems
- 5th Int. Conf. on High Performance and Embedded Architectures and Compilers (HiPEAC’10
"... Abstract. We present Offload, a programming model for offloading parts of a C++ application to run on accelerator cores in a heterogeneous multicore system. Code to be offloaded is enclosed in an offload scope; all functions called indi-rectly from an offload scope are compiled for the accelerator c ..."
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Cited by 16 (6 self)
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Abstract. We present Offload, a programming model for offloading parts of a C++ application to run on accelerator cores in a heterogeneous multicore system. Code to be offloaded is enclosed in an offload scope; all functions called indi-rectly from an offload scope are compiled for the accelerator
Efficient Parallelization of Path Planning Workload on Single-chip Shared-memory Multicores
"... Abstract—Path planning problems greatly arise in many applications where the objective is to find the shortest path from a given source to destination. In this paper, we explore the comparison of programming languages in the context of parallel workload analysis. We characterize parallel versions of ..."
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Cited by 1 (1 self)
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of path plan-ning algorithms, such as the Dijkstra’s Algorithm, across C/C++ and Python languages. Programming language comparisons are done to analyze fine grain scalability and efficiency using a single-socket shared memory multicore processor. Architectural studies, such as understanding cache effects
Results 1 - 10
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404
