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34
Formal verification of the ARM6 micro-architecture
, 2002
"... This report describes the formal verification of the arm6 micro-architecture using the hol theorem prover. The correctness of the microprocessor design compares the micro-architecture with an abstract, target instruction set semantics. Data and temporal abstraction maps are used to formally relat ..."
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Cited by 8 (2 self)
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This report describes the formal verification of the arm6 micro-architecture using the hol theorem prover. The correctness of the microprocessor design compares the micro-architecture with an abstract, target instruction set semantics. Data and temporal abstraction maps are used to formally
Verification driven formal architecture and microarchitecture modeling
- in MEMOCODE
, 2007
"... Our ability to verify complex hardware lags far behind our capacity to design and fabricate it. We argue that this gap is partly due to the limitations of RTL models when used for verification. Higher level models such as SystemC and SystemVerilog aim to raise the level of abstraction to enhance des ..."
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Cited by 3 (1 self)
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designer productivity; however, they largely provide for executable but not analyzable descriptions. We propose the use of formally analyzable design models at two distinct levels above RTL: the architecture and the microarchitecture level. At both these levels, we describe concurrent units of data
Verifying ARM6 Multiplication
"... Abstract. The hol-4 proof system has been used to formally verify the correctness of the ARM6 micro-architecture. This paper describes the specification and verification of the multiply instructions. The processor’s implementation is based on the modified Booth’s algorithm. Correctness is defined us ..."
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Cited by 2 (0 self)
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Abstract. The hol-4 proof system has been used to formally verify the correctness of the ARM6 micro-architecture. This paper describes the specification and verification of the multiply instructions. The processor’s implementation is based on the modified Booth’s algorithm. Correctness is defined
Verifying Micro-Architecture Simulators using Event Traces
"... Contemporary micro-architecture research inherently relies on cycleaccurate simulators to test new ideas. Typical simulator implementations involve tens of thousands of lines of high-level code. Although general software engineering verification and validation techniques can be applied, the mere com ..."
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Contemporary micro-architecture research inherently relies on cycleaccurate simulators to test new ideas. Typical simulator implementations involve tens of thousands of lines of high-level code. Although general software engineering verification and validation techniques can be applied, the mere
Formal verification of explicitly parallel microarchitectures
, 1999
"... An emerging trend in microprocessor design is to move complexity from a machine's microarchitecture into its instruction-set architecture. This trend will allow compilers to express inter-instruction dependency information that current superscalar out-of-order machines, such as the Pentium III ..."
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An emerging trend in microprocessor design is to move complexity from a machine's microarchitecture into its instruction-set architecture. This trend will allow compilers to express inter-instruction dependency information that current superscalar out-of-order machines, such as the Pentium
Formal Verification of the AAMP-FV Microcode
, 1999
"... This report is organized as follows. Chapter 2 provides general background, describing the participants in the project, the history of the AAMP family of microprocessors, the PVS speci- #cation language, and a brief survey of related work. Chapter 3 discusses the goals and history of the project. Ch ..."
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. Chapter 4 describes the AAMP-FV instruction set #macro# architecture and its speci#cation in PVS. Chapter 5 provides a similar discussion of the AAMP-FV register transfer #micro# architecture. Chapter 6 describes the formal veri#cation e#ort. Chapter 7 discusses lessons learned on both the AAMP5 and AAMP
FORMAL HARDWARE VERIFICATION BY SYMBOLIC TRAJECTORY EVALUATION
, 1997
"... Formal verification uses a set of languages, tools, and techniques to mathematically reason about the correctness of a hardware system. The form of mathematical reasoning is dependent upon the hardware system. This thesis concentrates on hardware systems that have a simple deterministic high-level s ..."
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Cited by 18 (1 self)
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. An implemen-tation mapping is used to relate abstract states to detailed circuit states. The mapping captures the micro-architecture of an implementation of the processor. Symbolic Trajectory Evaluation is used to verify that the circuit fulfills each individual abstract assertion under the implementation
A Formal Verification of Ultrascalar Processor using Term Rewriting Systems
"... Introduction Today's microprocessors implement increasingly complex micro-architectures to achieve high performance. With increasing complexity, understanding the semantics of the instructions is more difficult. As a part of the processor design chain, verifying the correctness of a specificat ..."
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Introduction Today's microprocessors implement increasingly complex micro-architectures to achieve high performance. With increasing complexity, understanding the semantics of the instructions is more difficult. As a part of the processor design chain, verifying the correctness of a
Systematic Verification Of Pipelined Microprocessors
, 2000
"... This dissertation addresses the problem of formally verifying the correctness of pipelined microprocessors at the micro-architectural level of abstraction. Contemporary processor designs are highly complex, employing sophisticated performance enhancing techniques such as superscalar pipelining, out- ..."
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Cited by 11 (0 self)
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This dissertation addresses the problem of formally verifying the correctness of pipelined microprocessors at the micro-architectural level of abstraction. Contemporary processor designs are highly complex, employing sophisticated performance enhancing techniques such as superscalar pipelining, out
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