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Systematic Verification Of Pipelined Microprocessors

by Ravi Mohan Hosabettu , 2000
"... This dissertation addresses the problem of formally verifying the correctness of pipelined microprocessors at the micro-architectural level of abstraction. Contemporary processor designs are highly complex, employing sophisticated performance enhancing techniques such as superscalar pipelining, out- ..."
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This dissertation addresses the problem of formally verifying the correctness of pipelined microprocessors at the micro-architectural level of abstraction. Contemporary processor designs are highly complex, employing sophisticated performance enhancing techniques such as superscalar pipelining, out

A scalable formal verification methodology for pipelined microprocessors

by Jeremy Levitt , Kunle Olukotun , Jeremy Levitt , Kunle Olukotun - In Proceedings of the 33rd Conference on Design Automation (Las Vegas, NV , 1996
"... Abstract We describe a novel, formal verification technique for proving the correctness of a pipelined microprocessor that focuses specifically on pipeline control logic. We iteratively deconstruct a pipeline by merging adjacent pipeline stages, allowing for the verification to be done in several e ..."
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Abstract We describe a novel, formal verification technique for proving the correctness of a pipelined microprocessor that focuses specifically on pipeline control logic. We iteratively deconstruct a pipeline by merging adjacent pipeline stages, allowing for the verification to be done in several

Trace Table Based Approach for Pipelined Microprocessor Verification

by Jun Sawada, Warren A. Hunt, Jr. , 1997
"... This paper presents several techniques for formally verifying pipelined microprocessor implementations that contain out-of-order execution and dynamic resolution of data-dependent hazards. Our principal technique models the trace of executed instructions using a tablebased representation called ..."
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This paper presents several techniques for formally verifying pipelined microprocessor implementations that contain out-of-order execution and dynamic resolution of data-dependent hazards. Our principal technique models the trace of executed instructions using a tablebased representation called

Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors

by Miroslav N. Velev, Randal E. Bryant - In Design Automation Conference , 1999
"... We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2][3] to the verification of pipelined microprocessors with very large Instruction Set Architectures (ISAs). Abstraction of memory arrays and functional units is employed, while the control logic of the ..."
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We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2][3] to the verification of pipelined microprocessors with very large Instruction Set Architectures (ISAs). Abstraction of memory arrays and functional units is employed, while the control logic

Verifying Pipelined Microprocessors

by Phillip J. Windley - In Proceedings of the 1995 IFIP Conference on Hardware Description Languages and their Applications (CHDL , 1995
"... Recently there has been much research in verifying pipelined microprocessors. Even so, there has been little consensus on what form the correctness statement should take. Put another way, what should we be verifying about pipelined microprocessors? We believe that the correctness statement should ..."
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written over the years regarding the formal specification and verification of microprocessors. Most of these efforts have been directed at non--pipelined microprocessors. In nearly all of these proofs, the final results, or correctness statement had the form: 8s: I(s) ) B(A(s)) where s is the state

Term-Level Verification of a Pipelined CISC Microprocessor

by Randal E. Bryant , 2005
"... By abstracting the details of the data representations and operations in a microprocessor, term-level verification can formally prove that a pipelined microprocessor faithfully implements its sequential, instruction-set architecture specification. Previous efforts in this area have focused on reduce ..."
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By abstracting the details of the data representations and operations in a microprocessor, term-level verification can formally prove that a pipelined microprocessor faithfully implements its sequential, instruction-set architecture specification. Previous efforts in this area have focused

Applying Formal Verification to a Commercial Microprocessor

by Mandayam K. Srivas, Steven P. Miller - In Computer Hardware Description Languages , 1995
"... Formal verification using interactive proof-checkers has been used successfully to verify a wide variety of moderate-sized hardware designs. The industry is beginning to look at formal verification as an alternative to simulation for obtaining higher assurance than is currently possible. However, ma ..."
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Avionics, a division of Rockwell International to explore some of these questions. The project formally specified in SRI's PVS language a Rockwell proprietary pipelined microprocessor (the AAMP5, built using almost half a million transistors) at both the instruction-set and register-transfer levels

Specification and Verification of Pipelining in the ARM2 RISC Microprocessor

by James K. Huggins, David Van Campenhout - ACM Transactions on Design Automation of Electronic Systems , 1997
"... State Machines (ASMs) provide a sound mathematical basis for the specification and verification of systems. An application of the ASM methodology to the verification of a pipelined microprocessor (an ARM2 implementation) is described. Both the sequential execution model and final pipelined model are ..."
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State Machines (ASMs) provide a sound mathematical basis for the specification and verification of systems. An application of the ASM methodology to the verification of a pipelined microprocessor (an ARM2 implementation) is described. Both the sequential execution model and final pipelined model

Verifying correct pipeline implementation for microprocessors

by Jeremy Levitt , Kunle Olukotun , Jeremy Levitt , Kunle Olukotun - In ICCAD ’97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design , 1997
"... Abstract We introduce a general, automatic verification technique for pipelined designs. The technique is based on a scalable, formal methodology for analysing pipelines. ..."
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Abstract We introduce a general, automatic verification technique for pipelined designs. The technique is based on a scalable, formal methodology for analysing pipelines.

Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors

by Miroslav N. Velev - Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems , 2001
"... A system of conservative transformation rules is presented for abstracting memories whose forwarding logic interacts with stalling conditions for preserving the memory semantics in microprocessors with in-order execution. Microprocessor correctness is expressed in the logic of Equality with Uninterp ..."
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exactly the same pair of one read and one write address is compared for equality in the stalling logic. These transformations are applied entirely automatically by a tool for formal verification of microprocessors, based on EUFM, the Burch and Dill flushing technique [6], and the properties of Positive
Results 1 - 10 of 43