Results 1 - 10 of 43

Shared memory consistency models: A tutorial

by Sarita V. Adve, Kourosh Gharachorloo - IEEE Computer , 1996
"... Parallel systems that support the shared memory abstraction are becoming widely accepted in many areas of computing. Writing correct and efficient programs for such systems requires a formal specification of memory semantics, called a memory consistency model. The most intuitive model—sequential con ..."
Abstract - Cited by 441 (10 self) - Add to MetaCart
—sequential consistency—greatly restricts the use of many performance optimizations commonly used by uniprocessor hardware and compiler designers, thereby reducing the benefit of using a multiprocessor. To alleviate this problem, many current multiprocessors support more relaxed consistency models. Unfortunately

The Semantics of Power and ARM Multiprocessor Machine Code

by Jade Alglave, Anthony Fox, Samin Ishtiaq, Magnus O. Myreen, Susmit Sarkar, Peter Sewell
"... We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets. The semantics is mechanised in the HOL proof assistant. This should provide a good basis for informal reasoning and for ..."
Abstract - Cited by 30 (6 self) - Add to MetaCart
We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets. The semantics is mechanised in the HOL proof assistant. This should provide a good basis for informal reasoning

S.: Theory of multi core hypervisor verification

by Ernie Cohen, Wolfgang Paul, Sabine Schmaltz - SOFSEM 2013, Theory and Practice of Computer Science. LNCS , 2013
"... Abstract. From 2007 to 2010, researchers from Microsoft and the Verisoft XT project verified code from Hyper-V, a multi-core x-64 hypervisor, using VCC, a verifier for concurrent C code. However, there is a significant gap between code verification of a kernel (such as a hypervisor) and a proof of c ..."
Abstract - Cited by 4 (1 self) - Add to MetaCart
Abstract. From 2007 to 2010, researchers from Microsoft and the Verisoft XT project verified code from Hyper-V, a multi-core x-64 hypervisor, using VCC, a verifier for concurrent C code. However, there is a significant gap between code verification of a kernel (such as a hypervisor) and a proof

Formal Verification of Delayed Consistency Protocols

by Fong Pong, Michel Dubois - In Proceedings of the 10th International Parallel Processing Symposium , 1996
"... In a cache-coherent, shared-memory multiprocessor system, data consistency among cached copies can be delayed until synchronization points under relaxed memory consistency models. Some protocols called delayed consistency protocols take advantage of this flexibility to reduce cache miss rates and me ..."
Abstract - Cited by 8 (4 self) - Add to MetaCart
In a cache-coherent, shared-memory multiprocessor system, data consistency among cached copies can be delayed until synchronization points under relaxed memory consistency models. Some protocols called delayed consistency protocols take advantage of this flexibility to reduce cache miss rates

Verification of Chip Multiprocessor Memory Systems Using A Relaxed Scoreboard

by Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz
"... Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to validate memory system implementation. Having a memory scoreboard, a high-level model of the memory, greatly aids simulat ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to validate memory system implementation. Having a memory scoreboard, a high-level model of the memory, greatly aids

Understanding POWER Multiprocessors

by Susmit Sarkar, Peter Sewell, Jade Alglave, Luc Maranget Derek Williams
"... Exploiting today’s multiprocessors requires highperformance and correct concurrent systems code (optimising compilers, language runtimes, OS kernels, etc.), which in turn requires a good understanding of the observable processor behaviour that can be relied on. Unfortunately this critical hardware/s ..."
Abstract - Cited by 43 (11 self) - Add to MetaCart
/software interface is not at all clear for several current multiprocessors. In this paper we characterise the behaviour of IBM POWER multiprocessors, which have a subtle and highly relaxed memory model (ARM multiprocessors have a very similar architecture in this respect). We have conducted extensive experiments

Nova Micro-Hypervisor Verification Formal, machine-checked verification of one module of the kernel source code (Robin deliverable D.13)

by Hendrik Tews, Tjark Weber, Marcus Völp, Erik Poll, Marko Eekelen, Peter Rossum , 2008
"... This document describes our achievements in work package 4 (kernel specification and verification) of the Robin project towards the verification of selected parts of the Nova micro-hypervisor. Despite organizational difficulties that were beyond our control (see below) we were able to finish our tas ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
-typed memory therefore rest only on properties that the Nova hypervisor itself ensures and not on additional assumptions. 2. A formal semantics in PVS of a sufficiently rich subset of C++, see Section 4.7.

An Axiomatic Memory Model for POWER Multiprocessors

by Sela Mador-haim, Susmit Sarkar, Jade Alglave, Rajeev Alur, Milom. K. Martin, Peter Sewell - In CAV , 2012
"... Abstract. The growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and disallowed behaviors, posing challenges in specifying their memory models formally and accurately, and in understanding and analyzing the behavior of concurrent softw ..."
Abstract - Cited by 21 (6 self) - Add to MetaCart
Abstract. The growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and disallowed behaviors, posing challenges in specifying their memory models formally and accurately, and in understanding and analyzing the behavior of concurrent

Litmus: Running Tests Against Hardware

by Jade Alglave, Luc Maranget, Susmit Sarkar, Peter Sewell
"... Abstract. Shared memory multiprocessors typically expose subtle, poorly understood and poorly specified relaxed-memory semantics to programmers. To understand them, and to develop formal models to use in program verification, we find it essential to take an empirical approach, testing what results p ..."
Abstract - Cited by 16 (8 self) - Add to MetaCart
Abstract. Shared memory multiprocessors typically expose subtle, poorly understood and poorly specified relaxed-memory semantics to programmers. To understand them, and to develop formal models to use in program verification, we find it essential to take an empirical approach, testing what results

Memory Consistency and Program Verification

by Rodrigo Ferreira , 2010
"... Formal reasoning about concurrent programs is usually done with the assumption that the underlying memory model is sequentially consistent, i.e. the execution outcome is equivalent to an interleaving of instructions according to the program order. However, memory models in reality are weaker in orde ..."
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in order to accommodate compiler and hardware optimizations. To simplify the reasoning, many memory models provide a guarantee that data-race-free programs behave in a sequentially consistent manner, the so-called DRF-guarantee. The DRF-guarantee removes the burden of reasoning about relaxations when
Results 1 - 10 of 43