Results 1 - 10 of 154

Microprocessors

by Trevor Meyerowitz, Student Member, Ieee Jonathan Sprinkle, Alberto Sangiovanni-vincentelli
"... Abstract — We detail the syntax and semantics of ISA_ML, a visual modeling language for describing Instruction Set Achitectures of microprocessors, and an accompanying tool that takes a description in the language and generates decoders from it in the form of a disassembler and a micro-architectural ..."
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Abstract — We detail the syntax and semantics of ISA_ML, a visual modeling language for describing Instruction Set Achitectures of microprocessors, and an accompanying tool that takes a description in the language and generates decoders from it in the form of a disassembler and a micro-architectural

Timing Anomalies in Dynamically Scheduled Microprocessors

by Thomas Lundqvist, Per Stenström
"... Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wrong in dynamically scheduled processors. A cache miss, for example, can in some cases result in a shorter execution time ..."
Abstract - Cited by 148 (0 self) - Add to MetaCart
than a cache hit. Many examples of such timing anomalies are provided. We first provide necessary conditions when timing anomalies can show up and identify what architectural features that may cause such anomalies. We also show that analyzing the effect of these anomalies with known techniques results

The design of an asynchronous MIPS R3000 microprocessor

by Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nystrom, Paul Penzes, Robert Southworth, Uri Cummings, Tak Kwan Lee - in Advanced Research in VLSI , 1997
"... The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0:6 m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, ..."
Abstract - Cited by 42 (5 self) - Add to MetaCart
The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0:6 m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches

Design of a Microsoft Version of MIPS Microprocessor Simulator

by Mohammad A. Mikki, Mohammed R. El-khoudary
"... ABSTRACT: We describe the implementation of a MIPS Simulator called MIPS-SIM. MIPS-SIM is a GUI, Java-based simulator for the MIPS assembly language. MIPS, the computer architecture is widely used in industry and is the basis of the popular textbook Computer Organization and Design by David Patterso ..."
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ABSTRACT: We describe the implementation of a MIPS Simulator called MIPS-SIM. MIPS-SIM is a GUI, Java-based simulator for the MIPS assembly language. MIPS, the computer architecture is widely used in industry and is the basis of the popular textbook Computer Organization and Design by David

MIPS16: High-density MIPS for the Embedded Market,

by Kevin D Kissell - in Proceedings of Real Time Systems'97 (RTS97), , 1997
"... Origins of MIPS® RISC Technology The invention of RISC, or Reduced Instruction Set Computer technology, has been credited to several people. Certainly a great deal of the credit must go to John Cocke of IBM's Yorktown research labs, where a processor called the 801 (named for the building in w ..."
Abstract - Cited by 47 (0 self) - Add to MetaCart
correctly. Hennessy and his team were pleased enough with the results that they founded MIPS Computer in 1984 to commercialize what was then becoming known as RISC technology. MIPS is now a subsidiary of Silicon Graphics, Inc., and the MIPS architecture is perhaps the most widely known and used RISC. 1. A

The Design of an Asynchronous MIPS R3000 Microprocessor

by Alain Martin Andrew, Andrew Lines, Rajit Manohar, Mika Nystrom, Paul Penzes, Robert Southworth, Uri Cummings, Tak Kwan Lee - in Advanced Research in VLSI , 1997
"... The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0:6m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, a ..."
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The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0:6m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches

Spert-II: A Vector Microprocessor System

by John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan , 1996
"... this article. Primary support for our work came from ONR URI Grant N00014-92-J-1617, ARPA Contract N0001493-C0249, NSF Grant MIP-9311980, and NSF PYI AwardMIP-8958568NSF.Additional support was provided by ICSI. IBM donated the RS/6000. ..."
Abstract - Cited by 60 (8 self) - Add to MetaCart
this article. Primary support for our work came from ONR URI Grant N00014-92-J-1617, ARPA Contract N0001493-C0249, NSF Grant MIP-9311980, and NSF PYI AwardMIP-8958568NSF.Additional support was provided by ICSI. IBM donated the RS/6000.

Vector microprocessors

by For Cryptography, Jacques Jean-alain Fournier, Cambridge Cb Fd , 2007
"... Embedded security devices like ‘Trusted Platforms ’ require both scalability (of power, performance and area) and flexibility (of software and countermeasures). This thesis illustrates how data parallel techniques can be used to implement scalable architectures for cryptography. Vector processing is ..."
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is used to provide high performance, power efficient and scalable processors. A programmable vector 4-stage pipelined co-processor, controlled by a scalar MIPS compatible processor, is described. The instruction set of the co-processor is defined for cryptographic algorithms like AES and Montgomery

RISC Microprocessor

by James Montanaro, Richard T. Witek, Krishna Anne, Andrew J. Black, Elizabeth M. Cooper, Daniel W. Dobberpuhl, Paul M. Donahue, Jim Eno, David Kruckemyer, Thomas H. Lee, Peter C. M. Lin, Liam Madden, Daniel Murray, Mark H. Pearce, Sribalan Santhanam, Kathryn J. Snyder, Ray Stephany, Stephen C. Thierauf, Associate Member
"... Abstract — This paper describes a 160 MHz 500 mW StrongARM ®1 microprocessor designed for low-power, low-cost applications. The chip implements the ARM ® V4 instruction set [1] and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can var ..."
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Abstract — This paper describes a 160 MHz 500 mW StrongARM ®1 microprocessor designed for low-power, low-cost applications. The chip implements the ARM ® V4 instruction set [1] and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can

A Complementary GaAs Microprocessor for Space Applications

by Todd D. Basso, Richard B. Brown - Proc. of The Second International Conference on Integrated Micro-Nanotechnology for Space Applications, November 1-3,1998, CDROM 98p25a.pdf
"... Abstract—This paper describes the development of a complementary GaAs PowerPC TM microprocessor suitable for space applications. Motorola’s 0.5μm Complementary GaAs (CGaAs TM) process was selected as the semiconductor technology because of its unique abilities to meet the requirements of space and s ..."
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is guided by a small two-level dynamic branch prediction mechanism. Computation is performed by a small superscalar execution core. The architecture, running at 200MHz, is capable of achieving 153 MIPS, translating to a 27 % performance increase over a comparable traditional pipelined microprocessor
Results 1 - 10 of 154