Recent studies have concluded that little parallelism (less than two operations per cycle) is available in single instruction streams. Since the amount of available parallelism should influence the design of the processor, it is important to verify how much parallelism really exists. In this study

We describe the design and implementation of Dynamo, a software dynamic optimization system that is capable of transparently improving the performance of a native instruction stream as it executes on the processor. The input native instruction stream to Dynamo can be dynamically generated (by a JIT

This paper describes a system software design for multiple instruction stream control in a massively parallel associative computing environment. The purpose of providing multiple instruction stream control is to increase throughput and reduce the amount of parallel slackness inherent in single

Differential power analysis (DPA) has become a real-world threat to the security of cryptographic hardware devices such as smart-cards. By using cheap and readily available equipment, attacks can easily compromise algorithms running on these devices in a non-invasive manner. Adding non-determinism to the execution of cryptographic algorithms has been proposed as a defence against these attacks. One way of achieving this non-determinism is to introduce random additional operations to the algorithm which produce noise in the power profile of the device. We describe the addition of a specialised processor pipeline stage which increases the level of potential non-determinism and hence guards against the revelation of secret information.

This report details the implimentation of a peephole optimiser stage for KROC (Kent Retargetable Occam Compiler)(Wood and Welch, 1996). 1 Introduction The KROC compiler has been ported to a variety of different architectures, e.g. Sparc, Alpha, PowerPC and Sharc. Benchmarking has shown that the performance of KROC is within a factor of between 2 and 4 of optimised C or assembly code. This performance bottleneck has previously been tackled by writing critical sections of code in either C or assembly language, and linking them with main OCCAM program. This situation is not Ideal, as it requires code profiling and considerable effort to hand code the critical regions. There has been speculation that significant benefit would be gained from peephole optimisation of the target assembly code produced by KROC. The report details an investigation into the potential gains of this target code optimisation. The compilation process for a KROC program has several stages, occ21 compiles OCCAM in...

This paper describes a single chip MultipleInstruction -Stream Multiple-Execution-Pipeline (MISMEP) architecture capable of improving processor throughput. The MIS-MEP architecture uses multiple instruction dispatch/branch units (slots) to dispatch instructions from multiple instruction streams

iterations or processes are executed in parallel on different processors to exploit loop-level parallelism and process-level parallelism. A new generation of architectures that execute multiple instruction streams on a single chip has the potential of significantly reducing the gap between communication

to hardware mechanisms for caching dynamic traces from the instruction stream. Recently, a technique to form long instruction sequences called frames using branch promotion has been proposed. Frames are instruction entities that can grow to be very long and must be cached as atomic units.

This paper describes a single chip MultipleInstruction -Stream Multiple-Execution-Pipeline (MISMEP) architecture capable of improving processor throughput. The MIS-MEP architecture uses multiple instruction dispatch/branch units (slots) to dispatch instructions from multiple instruction streams

The potential performance of superscalar processors can be exploited only when processor is fed with sufficient instruction bandwidth. The front-end units, the Instruction Stream Buffer (ISB) and the fetcher, are the key elements for achieving this goal. Current ISBs could not support instruction