"... In PAGE 18: ... In this case, longer adaption time is not a serious problem, because identification is done only once without any time constraints. Table3 summarizes the memory length and the required filter operations for the nonlinear filter part for both realizations. Even though the memory length of the MMD filter is twice as long, the number of filter operations in the identification phase is similar to that of the general Volterra case.... ..."

"... In PAGE 2: ... Table1 . Computational complexity of 5th-order Volterra inverse... ..."

"... In PAGE 13: ...2. Identification of NLSs with memory Table2 shows the eigenvalue spread of the functional covariance matrix of several Volterra and Fourier models with Q=2, for orders N={5, 10} and for the same input distributions of Table 1. As in the previous subsection, the superiority of the Fourier model is evident.... ..."

"... In PAGE 20: ... With these quantities available, we may compute the theoretical MMSE for the lters. This is done in Table1 for fully coupled Volterra lters and partially decoupled Volterra lters operating with signal-to-noise ratios (SNRs) of 0dB, 5dB, and 10dB, where... In PAGE 20: ...Table1... ..."

"... In PAGE 3: ... First, define the squared sum of the pth-order kernel coeffi- cients of wavelet filter length C6 as BV B4D4B5 C6 BP BEC6A0BE CG D1 BD BPA0B4BEC6A0BEB5 A1A1A1 BEC6A0BE CG D1 D4 BPA0B4BEC6A0BEB5 CYCW D4 CJD1 BD BN A1A1A1 BND1 D4 CLCY BE (17) and the squared sum of the truncated pth-order kernel coefficients of memory length C3 as BV B4D4B5 C3 BP B4C3A0BDB5BPBE CG D1 BD BPA0B4C3A0BDB5BPBE A1A1A1 B4C3A0BDB5BPBE CG D1 D4 BPA0B4C3A0BDB5BPBE CYCW D4 CJD1 BD BN A1A1A1 BND1 D4 CLCY BE (18) The ratio of the two squared sums, gives a measure of the approx- imation accuracy of the truncated pth-order kernel to the original kernel, denoted AC D4 AC D4 BP BV B4D4B5 C3 BV B4D4B5 C6 (19) where BC AK AC D4 AK BD. Table2 shows the values of AC BF and AC BH for the Daubechies and Symlets filters of length C6 BPBDBG. It can be seen from the tables that, for both truncated 3rd- and 5th-order Volterra kernels with memory length C3 BP BDBN BF and 5, the Symlets filter always results in a higher AC BF and AC BH ratios.... ..."

"... In PAGE 5: ... Additionally there are probabilities to determine whether members of either species will migrate to another cell. Table1 lists all the prob- abilities relating to a single time-step; these remain invariant throughout all the simulations. These parameter values were those used by Wol in his work, and have been chosen since they produce the desired Predator-Prey oscillations for a... ..."

"... In PAGE 3: ...-The oxidation of edta4- is first order in [Ag quot; apos;] at excess of edta4-. Values of kobs are listed in Table2 and plotted in Fig. 1.... ..."

"... In PAGE 26: ... However, some timing failures that are embedded in short paths may not cause delay faults at normal operating conditions. Table3 -1 lists the causes of timing failures and the possible testing techniques for detecting them. Although all of these failures may be detected by delay fault testing, the success of detection depends on the significance of the excessive delay in the defective circuit.... In PAGE 27: ... We verified these findings for both failure modes by investigating the delay flaws caused by transmission gate opens, threshold voltage shifts, and diminished-drive gates. Table3 -1 Testing Techniques for Timing Failures Causes at transistor level Detected by Transmission gate opens V* D** Threshold voltage shifts V D Diminished-drive gates V D Gate oxide shorts V D I*** Metal shorts V D I Defective interconnect buffers V D I High resistance interconnects, via defects D Tunneling opens D * VLV Testing, **Delay Fault Testing, ***IDDQ Testing 3.1 Causes and Failure Modes of Timing Failures Table 3-1 lists the causes of timing failures.... In PAGE 27: ... Table 3-1 Testing Techniques for Timing Failures Causes at transistor level Detected by Transmission gate opens V* D** Threshold voltage shifts V D Diminished-drive gates V D Gate oxide shorts V D I*** Metal shorts V D I Defective interconnect buffers V D I High resistance interconnects, via defects D Tunneling opens D * VLV Testing, **Delay Fault Testing, ***IDDQ Testing 3.1 Causes and Failure Modes of Timing Failures Table3 -1 lists the causes of timing failures. Transmission gate opens occur when one of the transistors in a CMOS transmission gate is malfunctioning and cannot pass any signals.... In PAGE 28: ... Tunneling opens allow CUTs to be functional at low frequencies but cause failures at higher frequencies [Henderson 91]. Table3 -2 summarizes the failure modes of the timing failures described above. This chapter discusses how VLV testing can improve the detectability of timing failures that are caused by degraded signals and by transistors with lowered driving capabilities.... In PAGE 29: ... Table3 -2 Failure Modes of Timing Failures Causes Failure Modes Transmission gate opens Degraded signals Threshold voltage shifts Increased gate delays Slow-to-fall signals Diminished-drive gates Increased gate delays Slow-to-rise signals Slow-to-fall signals Gate oxide shorts Degraded signals Increased leakage Metal shorts Degraded signals Increased leakage Defective interconnect buffers Degraded signals Increased gate delays Increased RC delays Increased leakage Opens High resistance interconnects, via defects Increased RC delays Slow-to-rise signals Slow-to-fall signals Tunneling opens CUT fails at high frequencies 3.2 Voltage Dependence of CMOS Propagation Delay VLV testing is most effective in detecting delay flaws when the supply voltage is around the value where the propagation delay of a circuit starts to change significantly as the supply voltage is reduced.... In PAGE 31: ...5Vt, which is the same as the voltage range for VLV testing proposed in Chapter 2. Table3 -3 lists the delay ratios of WD and fault-free gates at different voltages for... In PAGE 35: ...nd the 0.6 m m technology are similar, only the results for the 0.6 m m technology are discussed in this dissertation. Table3 -4 shows the simulation results for the 0.6 m m technology.... In PAGE 36: ... Table3 -4 Delay Ratio between Faulty and Fault-Free High-Drive Gate in Fig. 3-3 for the 0.... ..."