"... In PAGE 7: ... It can be observed from this figure that the probability distribution has very high density in a relatively small area in the voltage drop domain, and vanishes rapidly outside this area. Table1 illustrates results where a number of nodes critical nodes were randomly selected to be critical, and the proba- bility of timing violations was calculated using our method. In this table, we compare the proposed column-sampling approach for the estimation of the covariance matrix of crit- ical nodes ( Sampling ), with the result of calculating the entries of this matrix by full solution of (18) ( Solution ).... ..."

"... In PAGE 5: ... CPU time for Flow VIIa and VIIb are the sum of the initial routing time (before scan-insertion) and the final routing time (after the scan-insertion). Table6 shows the effect on timing violations and slacks. We use setup violations for the timing measurements.... In PAGE 5: ... completes the routing with violations; however, with these cases, the industry flow has violations as well. In the timing domain ( Table6 ), although our current flow does not consider slacks in the cost matrix calculation, we see a reduction in the number of timing violations. In addition, the magnitudes of the timing violations (i.... ..."

"... In PAGE 9: ... Tests associated with corresponding crosstalk delay that cause timing violations at POs are recorded so that the test creating the worst case timing violation at a PO can be identified. The results are shown in Table3 . All units are in pico second.... In PAGE 9: ... The results correlate well with SPICE simulations. The timing criteria in Table3 is the longest path delay of the circuit plus an extra delay slack of one gate delay. In Table 3 we can see that if there is no crosstalk effect (Cm = 0), then there is no timing violation at any primary output.... In PAGE 9: ... The timing criteria in Table 3 is the longest path delay of the circuit plus an extra delay slack of one gate delay. In Table3 we can see that if there is no crosstalk effect (Cm = 0), then there is no timing violation at any primary output. As we increase the coupling capacitance, the victim line signal become more delayed and its transition time increases.... ..."

"... In PAGE 7: ...7 parameters are listed in Table1 , and have been calculated from [22]. The delay estimation engine is ultimately used to check for bus cycle time violations in the design.... ..."

"... In PAGE 6: ... Figure 14. Final floorplan for derivative SoC subsystem Table5 compares the final synthesized designs for the two case studies with the results for the initial single main/peripheral shared bus mapped design, a synthesis flow without floorplanner and timing violation detection, and a manual synthesis effort by a designer. Compared with the initial design, the final synthesized design not only performs significantly better but also satisfies all constraints.... ..."

"... In PAGE 6: ... Figure 14. Final floorplan for derivative SoC subsystem Table5 compares the final synthesized designs for the two case studies with the results for the initial single main/peripheral shared bus mapped design, a synthesis flow without floorplanner and timing violation detection, and a manual synthesis effort by a designer. Compared with the initial design, the final synthesized design not only performs significantly better but also satisfies all constraints.... ..."

"... In PAGE 15: ... In this example each HOMEBOT will have a utility function as described by Eq. (1) with f i #28r#29 = 0 when the consumption is such that the disconnection time, as defined in Table2 , is not violated, and f i #28r#29 = ,C,whereC is a large constant, otherwise. That is, as long as the contracted disconnection time is not violated, there is no cost for the load management, but if the contract is violated there is a very high cost.... ..."